Cisco Documents Shed Light on Cascade Lake, Cooper Lake, and Ice Lake for Servers
by Ian Cutress on February 5, 2019 9:25 AM EST- Posted in
- CPUs
- Intel
- Cisco
- Enterprise CPUs
- Ice Lake
- Cascade Lake
- Cooper Lake
In a publicly available document, found by an eagle-eyed user on Twitter, Cisco has revealed some details about the future Whitley Platform and Barlow Pass: the set of technologies on which Cooper Lake and Ice Lake Xeon Scalable will be based.
The document detailing Cisco’s Unified Computing System, was published in December 2018 for Cisco customers to plan their future upgrade strategy. The document focuses on Cisco’s networking portfolio, as one might have assumed, but also shows a roadmap on the company’s current M5 server platform and the upcoming M6 platform.
Cisco is listing its M6 server platform, for Cooper Lake and Ice Lake, as expecting to be launched in the first half of 2020. This is on par with our estimates, although perhaps a bit slow for Cooper Lake given that Intel has already shown roadmaps indicating that Cooper Lake is a 2019 platform (clearly, a late 2019).
The Whitley Platform will follow the Purley Platform, and this document confirms that Whitley (which has both Cooper Lake and Ice Lake in support) will have 8 channels of DDR4 supporting up to DDR4-2933 memory. This will require a new socket for the extra channels, which we know as LGA4189, and will put Intel on par with AMD’s EPYC platform in channel count.
The document also sheds some light on Intel’s PCIe strategy. We have already seen that AMD will launch its new Rome processors in 2019 with PCIe 4.0 support, and Intel will follow that with Cooper Lake and Ice Lake, however it looks as if Intel will bifurcate this strategy. This document lists Cooper Lake as PCIe 3.0/4.0, which might suggest that there will be two different versions, or that it will be rated PCIe 3.0 to start and 4.0 will come later. We are not sure, however it does list Ice Lake as PCIe 4.0 out of the gate.
It is worth noting that the motherboards for Whitley will support Cooper Lake and Ice Lake, so they will have to cater for PCIe 4.0 straight out of the gate. If Cooper Lake does come out with PCIe 3.0 only parts, we may see motherboards that only support PCIe 3.0 for specific customers (much like when we have a DDR memory change). This is unclear at this point.
It is worth noting that this document misspells Cooper Lake as Copper Lake. Given that this is an official document we expect this is only a typographical error. It also doesn't list the process technologies for Cooper and Ice, even though they had been announced in December. This is likely just a delay of information propagation.
Source: Cisco
Title image from Intel's Architecture Day, showing an Ice Lake Xeon Scalable LGA4189 processor
Related Reading
- Intel’s Keynote at CES 2019: 10nm, Ice Lake, Lakefield, Snow Ridge, Cascade Lake
- Intel Server Roadmap: 14nm Cooper Lake in 2019, 10nm Ice Lake in 2020
- Intel’s Xeon Scalable Roadmap Leaks: Cooper Lake-SP, Ice Lake-SP Due in 2020
- Power Stamp Alliance Exposes Ice Lake Xeon Details: LGA4189 and 8-Channel Memory
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Santoval - Tuesday, February 5, 2019 - link
AMD might wait for 2021 before adopting DDR5. Zen 2 is a new design and is released this year (with PCIe 4.0 but not DDR5). Zen 3 will apparently be released in 2020, but as it is an optimized Zen 2 and not a new design, I highly doubt it will support DDR5 either. Even if it did though (since apparently only -or mostly- new I/O dies with DDR5 memory controllers would be required), if AMD sticks to their release of new server CPUs every odd year cadence, they are not going to release Zen 3 based server CPUs in 2020 anyway, so there would be little need to rush DDR5 adoption.Adoption of DDR5 in 2021 with Zen 4, the next new Zen design, appears to be much more practical. 2021 is also beyond the year (2020) that AMD guaranteed backwards socket compatibility, so they will be free to adopt new sockets with more pins, more memory channels (if required, since DDR5 might not need them) and by and large design their platforms from a clean slate.
Death666Angel - Tuesday, February 5, 2019 - link
You kinda provided an argument against your own statement, didn't you? :D AMD has been very good at the chiplet thing and mixing and matching certain IP blocks (DDR3 and GDDR5 support with last consoles, Ryzen GDDR5 support with the Chinese console chip). And the IO chiplet approach points much more strongly towards them pursuing this trend. I expect Zen 3 or Zen2+ to be DDR4 and DDR5 compliant, much like a lot of current Intel CPUs support DDR4 but also LPDDR3 or something to that effect. It shouldn't add too much die area.rahvin - Wednesday, February 6, 2019 - link
The chiplet design gives AMD the ability to cycle/respin the IO chiplet and suddenly have PCIe4 and DDR5 or whatever else they want without repining the CPU chiplets. It actually makes them far more agile if they choose to be. If the supporting peripherals like shipping PCIe4 cards and DDR5 memory actually starts shipping at some point.Though both of those would require a new motherboard and associated chipset its actually probably easier for them to adjust the CPU at this point than the motherboard support.
Targon - Wednesday, February 6, 2019 - link
You will need a new socket to support a new memory type. While some processors themselves can support multiple sockets(such as when AMD made the jump from DDR2 to DDR3), the new socket would need to be designed with that in mind.Kevin G - Wednesday, February 6, 2019 - link
For server, it would only make sense to go to DDR5 if it provides a capacity increase right out of the gate with reasonable cost. Shrinks have progressed to a snail's pace on the CPU side but DRAM may not scale below 10 nm. Recent capacity increases have been obtained via die stacking or simply throwing more chips onto a DIMM.GreenReaper - Tuesday, February 5, 2019 - link
A copper lake would have been cooler - pair it with an ice lake reservoir and you could OC to the moon!Lord 666 - Tuesday, February 5, 2019 - link
This is not an Intel cpu roadmap but a presentation fail. Check out page 23, it clearly says “Processor timeline and availability based on Intel disclosure to Cisco on April 2017. Subject to change.” April 2017!!!drunkenmaster - Wednesday, February 6, 2019 - link
Keep in mind that what Intel say privately in meetings to the big OEMs isn't always, or even often, what they are saying publicly to investors/conference calls and in announcements. You can get away with lying about 10nm to investors (though you shouldn't ) and making promises at CES/Computex, etc, but if you mess around with the server guys so they don't have time to prepare for your platforms then you're going to lose billions and billions in business by messing them around. Also keep in mind that based on information from April 2017, they are saying 10nm server is coming likely very end of 2020, publicly Intel was still promising 10nm would ramp throughout 2018 at the end of 2017 and that would mean desktop and server before the end of 2018. yet this business that sells servers was told in 2017 to not expect 10nm servers till at least 2 years later.JlHADJOE - Wednesday, February 6, 2019 - link
Man even Ice Lake is *still* DDR4? Was hoping to hold off on upgrades till DDR5 but it seems like it's still a long way till launch.SarahKerrigan - Wednesday, February 6, 2019 - link
Purley didn't have a very long platform lifetime, did it? Skylake-SP and the relatively small Cascade-SP kicker. Compared to Brickland (Ivy-EX, Haswell-EX, Broadwell-EX), that's pretty underwhelming.