Today Intel’s CEO Pat Gelsinger has outlined two key changes to Intel policy: one derived from Intel’s plans to offer foundry services to external partners, and the other from Intel starting to outsource its core compute product families in order to get the best product at a given time. Not only is Intel set to offer x86 core IP to customers through its new Intel Foundry Services, but also Intel is looking to creating leadership compute products on external nodes. These are complete 180º turns from how Intel has previously operated.

For the last 20-25 years, Intel has been steadfast in keeping the crown jewels of its product design firmly inside its very protective walls. Over the years, Intel’s x86 designs have mostly led the market in leadership performance and power (except for Pentium 4 and Rocket Lake), and limiting use/production for Intel-only use has enabled the company to improve that design with laser focus, manufacturing not-withstanding. Keeping the cores for internal use only means that neither customers nor competitors were able to see the raw design specifications, and for a long time this has enabled Intel to keep key features, such as its branch predictors, away from all but the most prying eyes.

In a twist to the norm, Intel is now set to dissolve those walls keeping its x86 cores it itself.

First up is Intel’s Foundry Services, a second crack at offering external customers the ability to use Intel’s manufacturing facilities. Idle fabs are costly, and so with IFS, Intel wants to enable a revenue stream while at the time meeting global demand for semiconductors, especially as it pertains to local supply chain security and migrating the world’s semiconductor reliance away from Asia more into the USA and EU. IFS will stand as a separate business unit inside Intel.

As part of IFS, Intel will both offer raw manufacturing services, similar to a standard foundry like TSMC and Samsung, as well as its portfolio of IP to customers. This is a Big Deal™.  Intel will enable a fully vertical model with its IP portfolio, allowing customers to choose from x86 cores, graphics, media, display, AI, interconnect, fabric, packaging, and other critical foundational IP from other sources (such as Arm, RISC-V). The exact way in which customers will be able to license the IP will be announced in due course, but if Intel were to follow the Arm model, then Intel customers will get access to Intel’s 86 core designs.

Arm’s model is bidirectional: core IP and architecture IP. The first allows you to build an SoC with defined cores, while the latter allows you to build your own cores with the instruction set (like Apple does with Arm). When applied to Intel, with the core IP, a customer can build designs based on Intel’s x86 cores with their own or external interconnects, or in different configurations to Intel’s standard model that are more optimized for what that particular customer requires. At the minute Intel is set only to offer core IP licenses, not architecture IP licenses.

If we take this idea and extrapolate, we could very well see x86 cores combined with new memory controllers, active interposers with custom interconnects.

Intel has kind of done this before, although it was very much a walled garden. Intel offered foundry services almost 7 years ago, under then CEO Brian Krzanich, that allowed very select customers to build new SoC designs, with Intel's help, and only for very select pre-approved use cases. In that time, Intel's effort for a proper foundry business was, in Gelsinger's own words, 'weak'. The new model is set to be more open, as far as we're led to believe.

The only question becomes to what extent will Intel offer x86 cores. Will it be the latest cores designed internally, or would they be a couple of generations behind? Will those designs be offered on a variety of process nodes, or just on a singular process node? Would a customer be able to get a core IP license and build it at another fab? This is where the second part of the announcement comes in.

As part of today’s announcement, Intel has stated that it will be expanding its use of third-party foundry capacity. Pat Gelsinger highlighted that it would be leveraging its relationships with TSMC, GlobalFoundries, Samsung, and UMC, to enable the best manufacturing facilities for its leading edge product designs, from communications and connectivity to graphics and chiplets. This builds on the announcements made by former CEO Bob Swan last year in light of Intel's own troubles on its 7nm process. Today's announcements reaffirms Swan's messaging, given that at the time the word 'pragmatic' was used, so while this has probably been in the works in a while, it is good to get a clear confirmation. As part of this announcement, to quote:

‘Gelsinger said he expects Intel’s engagement with third-party foundries to grow and to include manufacturing for a range of modular tiles on advanced process technologies, including products at the core of Intel’s computing offerings for both client and data center segments beginning in 2023’

The key phrase here is ‘core of Intel’s compute offerings’. It could be interpreted in two ways: at the core of a CPU design is a CPU core, which would mean an x86 design unless Intel were to skew away from x86 (unlikely). The other alternative could be an IO chiplet, which is also a ‘core part’ of a compute offering. Paul Alcorn from Tom’s Hardware has confirmed from Intel that the key element here is ‘compute cores’, and although Intel hasn’t specifically said the ISA of those cores, we are set to believe that Intel does indeed mean x86.

This means that other foundries will have access to the floorplans of Intel’s x86 designs, which used to be a big no-no at Intel. Now in saying that, foundries often have strict NDA requirements that stop them sharing designs with customers, as you might expect, but it’s the fact that Intel is even letting another foundry build x86 cores that is the highlight of this announcement.

All-in-all, Pat Gelsinger is enabling a roadmap that allows Intel to pivot, and pivot hard. Steering the Intel behemoth is difficult at the best of times, however Pat’s arrival and enthusiasm has certainly made the company more comfortable in finding where its next generation of revenue is coming from.


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  • RanFodar - Tuesday, March 23, 2021 - link

    I'm surprised that Intel would also be open to RISC-V and ARM IPs. It seems that while the ship hasn't been turned to the right direction, the planning and execution will be ready.
  • Matthias B V - Tuesday, March 23, 2021 - link

    Well they might not want to refit all the 22/16/10nm Fabs and anyway probably have issues getting enough EUV scanners so that is the best way to make money. For controllers, IoT and automotive those nodes are enough...

    They also need to be very open to get any customers as so far that is not a thing. And who knows how much competition x86 gets in future anyway. So Fab business might be important. Or it is just a move to prepare in case they want to sell the Fabs.

    Guess the lack of scanners at the economic situation where people buy anything they can are part of the reason to use 7nm in 2023. Though I hoped for U-Series in 7nm parallel to whole lineup of RaptorLake in 10 nm by Q4/2022
  • Ian Cutress - Wednesday, March 24, 2021 - link

    Intel has stated that they don't see equipment as a limiting factor, even with the long EUV machine lead times.
  • fallaha56 - Wednesday, March 24, 2021 - link

    well they would say that but ASML's share price spike says otherwise

    many promises here but meantime let's just see how far behind or not Ice Lake SP is vs Epyc 3rd gen

    of course now TSMC has clear motivation not to be esp supportative to Intel as well
  • Matthias B V - Wednesday, March 24, 2021 - link

    That's an interesting statement that equipment is not limiting.

    I would have expected it is quite a factor especially with the change from DUV to EUV and ASML being the only option. They will get more chips of one wafer on 7nm/5nm and further but they have far more 14/10nm Fabs now and any time soon.

    I would have bet whoever gets enough EUV scanners wins as this leads to more customers and shipments and therefore money to spend R&D.

    Not to mention that it is not just Intel, TSMC and Samsung but also SK Hynix and Micron that will increase orders for EUV boosting DDR5, LPDDR5, HBM3 and GDDR7 production and efficiency/performance.
  • dotjaz - Wednesday, April 7, 2021 - link

    Is the tuxedo really a limiting factor when you don't have the social status or money to attend certain function? Intel is severely limited by its R&D, their EUV process isn't gonna be ready until late 2022, and they already have at least half a dozen EUV machines by now to enable around 20K WSPM initially. that's 6 million CPUs per month assuming a die size of 150sqmm (enough space to fit 10 Cove cores and 128EU Xe)
  • zamroni - Wednesday, March 24, 2021 - link

    X86 cisc architecture is basically garbage which was created to address low ram capacity of 1980s home computers, not for performance.
    It has good performance just because Intel could pour money to have more advanced manufacturing compared to other foundries.
  • Santoval - Wednesday, March 24, 2021 - link

    Since the long CISC macro-OP instructions of x86 CPUs started being RISC-ized internally to short μOPs the distinction between CISC and RISC is much less clearly defined. Sure, it would be better and more efficient to run from top to bottom RISC instructions without the need and overhead to translate the CISC instructions to RISC and then back to CISC, but we live in an imperfect world. If we want native RISC we get ARM or (soon) RISC-V :)
  • zamroni - Wednesday, March 24, 2021 - link

    Probably the win win solution will be processor that decodes x86 command into arm or riscv risc commands so operating system use either x86 or risc natively
  • ZoZo - Wednesday, March 24, 2021 - link

    That's very close to what Apple is doing. Their CPU isn't exactly decoding the x86 instructions because they would need an x86 license for that, but it has special instructions to accelerate the translation done in software. That's why x86 emulation on Rosetta 2 is so fast and Mac OS can effectively run either x86 or ARM.

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