TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it has over a dozen of customers with tens of designs eager to use the technology to make their integrated circuits.

The 7 nm node is a big deal for the foundry industry in general and TSMC in particular. When compared to the CLN16FF+ technology (TSMC’s most widely used FinFET process technology) the CLN7FF will enable chip designers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60%, or increase frequency by 30% (at the same complexity). So far, TSMC has taped out 18 customer products using the CLN7FF technology, more than 50 CLN7FF products will be taped out by the end of 2018.

Unlike TSMC’s CLN10FF, which is used by a limited number of customers for a limited number of mobile SoCs, the CLN7FF is expected to be used to build CPUs, GPUs, FPGAs, neural network processors, cryptocurrency mining accelerators, mobile SoCs and so on. This is important because demand for smartphones is slowing down and TSMC needs other customers to offset lower orders for mobile SoCs.

“So far, we have already favored out more than 18 customer products with good yield [and] performance,” said C. C. Wei, a Co-CEO and President of TSMC, during a conference call with financial analysts. “More than 50 products tape-outs has been planned by end of this year from applications across mobile, server CPU, network processor, gaming, GPU, PGA, cryptocurrency, automotive and AI. Our 7nm is already in volume production.”

TSMC’s CLN7FF process technology will rely on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. As a result, the world’s largest contract maker of semiconductors will be able to use existing manufacturing tools to make 7 nm chips. Meanwhile, to keep using DUV lithography the company and its customers have to use multipatterning (triple and quadruple patterning), which increases design and production costs as well as product cycles.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10%
Performance 40% 20% 30% ? higher
Area Reduction none >50% 70% >37% ~17%

Next year TSMC intends to introduce its first manufacturing tech that will use extreme ultraviolet lithography (EUVL) for select layers. The CLN7FF+ will be the company’s second-generation 7 nm fabrication process because of maximized design rules compatibility and because it will keep using DUV tools that TSMC uses today for its CLN7FF production. From a general PPA (power, performance, area) improvement point of view, TSMC expects its CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. Furthermore, TSMC’s EUV-based 7 nm technology could also feature higher performance and a tighter distribution of currents, but the company’s execs do not quantitate the improvements just now.

“Our N7+ silicon result today are very encouraging,” said Mr. Wei. “Not only we have demonstrated equivalent or better performance [and] yield on both 256 Mb SRAM and on product like test vehicle when compared to [the] N7 baseline, we have also demonstrated a tighter distribution of electrical parameters in the areas, where EUV is supplied.”

TSMC is on track to start HVM using its 7 nm EUV process technology in mid-2019. Going forward, the company will increase usage of ASML’s Twinscan NXE step and scan systems when it starts to process wafers using its CLN5 (5 nm) process technology in 2020. According to the co-CEO of TSMC, the EUV results have been encouraging so far: the company’s 256 Mb SRAM test chip is already made with a “consistent double-digit yield”, which is rather good for a technology that is two years away from HVM. The high-ranking executive of TSMC also noted that the EUV infrastructure in general has made a good progress in the recent quarters. In particular, the company observed lower pellicle defects, higher mask yields, and improved photoresists. 

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  • NICOXIS - Tuesday, April 24, 2018 - link

    I wonder what the first CPU or GPU on 7nm will be.
  • SaberKOG91 - Tuesday, April 24, 2018 - link

    I think in general the first designs to tape out on a new process are usually memories (e.g. Flash, DRAM) or an ARM low-power design. In this case, however, Xilinx has already announced plans to manufacture an FPGA/SoC on this node and AMD have announced a 7nm refresh of Vega and EPYC 2 will be on 7nm, so they might well be first.
  • Yojimbo - Tuesday, April 24, 2018 - link

    Memory is not made on cutting edge processes. It's too cost-sensitive. Also, the processes seem to be a little bit different, and all major memory makers operate their own fabs. Both flash and DRAM are currently transitioning from the "1X" to the "1Y" process.

    You are right about low-powered devices, though. They are usually the first on a new process. I don't know how much of that is because of the money able to be made in the high-end smartphone business and how much is because it's easier to get good yields on a low-powered device compared to a high-powered one.

    As far as who is first for volume production on TSMC's 7nm, I think it is almost certainly Apple's A12.

    AMD makes their CPUs at Global Foundries, I believe.
  • anexanhume - Tuesday, April 24, 2018 - link

    Mobile designs are also smaller and thus more tolerant of the yield issues a new process may have early on. Most of them are on the order of 100mm^2, whereas enthusiast GPUs can push 500mm^2.
  • SaberKOG91 - Tuesday, April 24, 2018 - link

    Sorry, I should have been clearer: memories are usually produced first as tests because their repeating layouts are a good way to assess the process. Obviously anything the needs to be cost-effective will be done on older processes. Though the delay for adopting new nodes for memories seems to be reducing these days.

    To quote Lisa Su from Ian's interview:

    "So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do."

    So yes, the Vega cards are the more likely target for TSMC with EPYC 2 being the likely target for GloFo. I was responding to 7nm in general. I also think that Nvidia will likely wait on 7nm given how much they invested in 12nm to make the dies for the V100 and its derivatives.
  • Singuy888 - Tuesday, April 24, 2018 - link

    Actually per extremetech's tour of goflo, they started that Vega 7nm will be a pipe cleaner for Goflo. Adoredtv said his source is telling him TSMC will get Zen 2 to make sure Epyc 2 is successful.
  • LurkingSince97 - Wednesday, April 25, 2018 - link

    When you say "memmories" you mean SRAM. SRAM is used early on. DRAM? No. You can't just build DRAM on this process. DRAM is dramatically different than DRAM, and it has hit the scaling wall long ago. just search google. Here is an example article : http://semiengineering.com/1xnm-dram-challenges/ No process that makes cutting edge logic like this one from TSMC makes DRAM.
  • LurkingSince97 - Wednesday, April 25, 2018 - link

    >>> DRAM is dramatically different than SRAM
  • Dragonstongue - Tuesday, April 24, 2018 - link

    AMD "generally" makes at GF because of wafer agreement, but they are "allowed" to make them wherever they see fit because of court case they settled with Intel a few years ago where AMD license for x86 is applicable wherever is deemed "permissible"

    generally AMD has used GF because of wafer agreement and Ngreedia uses TSMC because they do not want to go out of their way to be involved with anything AMD has a possible hand in ^.^
  • ZolaIII - Wednesday, April 25, 2018 - link

    Everyone uses mature nods for huge prints. AMD has a history of using hi performance SOI node's and by the looks of things TSMC is far behind it's initial projections while Samsung is way ahead meaning they will be available about the same time. Even GF is still behind those two it also has an advantage of being able to provide it on SOI wafers (if costumer demands so). As 7nm FinFET will be a long term node & SOI makes GF one's much more advanced regarding performance while all three use different tools & layed out design aren't cross compatible I am certain AMD will stick with GF and so will IBM which actually mostly developed it. Samsung also may jump in on SOI bandwagon so things does not look good for TSMC.

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