TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it has over a dozen of customers with tens of designs eager to use the technology to make their integrated circuits.

The 7 nm node is a big deal for the foundry industry in general and TSMC in particular. When compared to the CLN16FF+ technology (TSMC’s most widely used FinFET process technology) the CLN7FF will enable chip designers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60%, or increase frequency by 30% (at the same complexity). So far, TSMC has taped out 18 customer products using the CLN7FF technology, more than 50 CLN7FF products will be taped out by the end of 2018.

Unlike TSMC’s CLN10FF, which is used by a limited number of customers for a limited number of mobile SoCs, the CLN7FF is expected to be used to build CPUs, GPUs, FPGAs, neural network processors, cryptocurrency mining accelerators, mobile SoCs and so on. This is important because demand for smartphones is slowing down and TSMC needs other customers to offset lower orders for mobile SoCs.

“So far, we have already favored out more than 18 customer products with good yield [and] performance,” said C. C. Wei, a Co-CEO and President of TSMC, during a conference call with financial analysts. “More than 50 products tape-outs has been planned by end of this year from applications across mobile, server CPU, network processor, gaming, GPU, PGA, cryptocurrency, automotive and AI. Our 7nm is already in volume production.”

TSMC’s CLN7FF process technology will rely on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. As a result, the world’s largest contract maker of semiconductors will be able to use existing manufacturing tools to make 7 nm chips. Meanwhile, to keep using DUV lithography the company and its customers have to use multipatterning (triple and quadruple patterning), which increases design and production costs as well as product cycles.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10%
Performance 40% 20% 30% ? higher
Area Reduction none >50% 70% >37% ~17%

Next year TSMC intends to introduce its first manufacturing tech that will use extreme ultraviolet lithography (EUVL) for select layers. The CLN7FF+ will be the company’s second-generation 7 nm fabrication process because of maximized design rules compatibility and because it will keep using DUV tools that TSMC uses today for its CLN7FF production. From a general PPA (power, performance, area) improvement point of view, TSMC expects its CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. Furthermore, TSMC’s EUV-based 7 nm technology could also feature higher performance and a tighter distribution of currents, but the company’s execs do not quantitate the improvements just now.

“Our N7+ silicon result today are very encouraging,” said Mr. Wei. “Not only we have demonstrated equivalent or better performance [and] yield on both 256 Mb SRAM and on product like test vehicle when compared to [the] N7 baseline, we have also demonstrated a tighter distribution of electrical parameters in the areas, where EUV is supplied.”

TSMC is on track to start HVM using its 7 nm EUV process technology in mid-2019. Going forward, the company will increase usage of ASML’s Twinscan NXE step and scan systems when it starts to process wafers using its CLN5 (5 nm) process technology in 2020. According to the co-CEO of TSMC, the EUV results have been encouraging so far: the company’s 256 Mb SRAM test chip is already made with a “consistent double-digit yield”, which is rather good for a technology that is two years away from HVM. The high-ranking executive of TSMC also noted that the EUV infrastructure in general has made a good progress in the recent quarters. In particular, the company observed lower pellicle defects, higher mask yields, and improved photoresists. 

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  • BillBear - Wednesday, April 25, 2018 - link

    >Taiwan Semiconductor Manufacturing Company (TSMC) is likely to score record profits for 2018 as the company will be gradually ramping up volume production of 7nm process in the second half of the year to fulfill lucrative orders from Apple for fabricating A12 application processors for its 2018 new iPhone models and from Quacomm for processing its new-generation smartphone chips, according to industry sources.

  • basket687 - Tuesday, April 24, 2018 - link

    So Intel has now officially lost its manufacturing lead...
  • Wilco1 - Tuesday, April 24, 2018 - link

    Both TSMC and Samsung 10nm are already much denser than Intel 14nm even when using Intel's density metric (https://www.semiwiki.com/forum/content/6713-14nm-1... So Intel is now 2 process generations behind...
  • DeepLake - Wednesday, April 25, 2018 - link

    You cant post links properly and you cant even read your own content on which you base your argument
    Intel's 14nm process is significantly denser than the competing processes from GF/SS and TSMC, >1.5x. It has taken roughly 3 years for SS and TSMC to introduce 10nm processes that are only slightly denser than Intel's 14nm process.
  • Wilco1 - Wednesday, April 25, 2018 - link

    Nope, my link shows clearly that Intel's published 14nm density is 37.5 million transistors/mm^2, while TSMC 10nm does 60.3 mt/mm^2. That's more than 1.6 times as dense. Actual designs achieve close to that density on TSMC, but not on Intel 14nm, so the difference is even larger in real chips.
  • bcronce - Wednesday, April 25, 2018 - link

    Intel's 10nm is 100 mt/mm^2.

    TSMC 10nm is 60% denser than Intel's 14nm, but Intel's 10nm is 66% denser than TSMC's 10nm.

    As for actual production density, it's difficult to compare apples to apples because Intel makes different kinds of chips than TSMC. Chip designs can greatly affect density, plus some high performing chips leave unused space to help with cooling. I'm just saying there could be a bias in chip designs because TSMC fabs and Intel fabs that could easily account for resulting density differences.
  • Wilco1 - Wednesday, April 25, 2018 - link

    Given the delays 10nm may go into volume production as a + or ++ variant, so the final density is unknown. How it compares vs TSMC 10nm no longer matters since it now competes with TSMC's 7nm which does ~116 mt/mm^2.

    Yes there are many factors that affect density in real chips, not only the design itself but also all the process details. Historically Intel has used more restrictive design rules and faster cell libraries and that negatively affects density.
  • bcronce - Wednesday, April 25, 2018 - link

    Maybe they need to stop with the XXnm and go with mt/mm^2. That would make it more useful, even if not perfect.

    I've never been much of an Intel CPU fan boy, but their fab process has historically been the best by a long shot. As fun as it is to cheer for someone that is doing so well that no one can beat them at their game, it is nice to have competition.
  • psychobriggsy - Wednesday, April 25, 2018 - link

    Which is what he said, SS/TSMC 10nm is denser than Intel 14nm (and note that each + on that 14nm process trades a little density for higher clocks).

    Right now, Intel is on 14nm, and TSMC is starting 7nm, hence his two generations ahead comment (although really it's ~1.1 generations) - although Intel should (but not necessarily will) get to 10nm late this year, catching up to the 7nm.
  • Wilco1 - Saturday, April 28, 2018 - link

    That'll be 2019 now rather than late this year. And we don't know what it will be like when it finally releases, my guess is they need to relax the "hyperscaling" considerably to get it to work.

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