TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it has over a dozen of customers with tens of designs eager to use the technology to make their integrated circuits.

The 7 nm node is a big deal for the foundry industry in general and TSMC in particular. When compared to the CLN16FF+ technology (TSMC’s most widely used FinFET process technology) the CLN7FF will enable chip designers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60%, or increase frequency by 30% (at the same complexity). So far, TSMC has taped out 18 customer products using the CLN7FF technology, more than 50 CLN7FF products will be taped out by the end of 2018.

Unlike TSMC’s CLN10FF, which is used by a limited number of customers for a limited number of mobile SoCs, the CLN7FF is expected to be used to build CPUs, GPUs, FPGAs, neural network processors, cryptocurrency mining accelerators, mobile SoCs and so on. This is important because demand for smartphones is slowing down and TSMC needs other customers to offset lower orders for mobile SoCs.

“So far, we have already favored out more than 18 customer products with good yield [and] performance,” said C. C. Wei, a Co-CEO and President of TSMC, during a conference call with financial analysts. “More than 50 products tape-outs has been planned by end of this year from applications across mobile, server CPU, network processor, gaming, GPU, PGA, cryptocurrency, automotive and AI. Our 7nm is already in volume production.”

TSMC’s CLN7FF process technology will rely on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. As a result, the world’s largest contract maker of semiconductors will be able to use existing manufacturing tools to make 7 nm chips. Meanwhile, to keep using DUV lithography the company and its customers have to use multipatterning (triple and quadruple patterning), which increases design and production costs as well as product cycles.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10%
Performance 40% 20% 30% ? higher
Area Reduction none >50% 70% >37% ~17%

Next year TSMC intends to introduce its first manufacturing tech that will use extreme ultraviolet lithography (EUVL) for select layers. The CLN7FF+ will be the company’s second-generation 7 nm fabrication process because of maximized design rules compatibility and because it will keep using DUV tools that TSMC uses today for its CLN7FF production. From a general PPA (power, performance, area) improvement point of view, TSMC expects its CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. Furthermore, TSMC’s EUV-based 7 nm technology could also feature higher performance and a tighter distribution of currents, but the company’s execs do not quantitate the improvements just now.

“Our N7+ silicon result today are very encouraging,” said Mr. Wei. “Not only we have demonstrated equivalent or better performance [and] yield on both 256 Mb SRAM and on product like test vehicle when compared to [the] N7 baseline, we have also demonstrated a tighter distribution of electrical parameters in the areas, where EUV is supplied.”

TSMC is on track to start HVM using its 7 nm EUV process technology in mid-2019. Going forward, the company will increase usage of ASML’s Twinscan NXE step and scan systems when it starts to process wafers using its CLN5 (5 nm) process technology in 2020. According to the co-CEO of TSMC, the EUV results have been encouraging so far: the company’s 256 Mb SRAM test chip is already made with a “consistent double-digit yield”, which is rather good for a technology that is two years away from HVM. The high-ranking executive of TSMC also noted that the EUV infrastructure in general has made a good progress in the recent quarters. In particular, the company observed lower pellicle defects, higher mask yields, and improved photoresists. 

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  • ianmills - Tuesday, April 24, 2018 - link

    I don't think the 7nm vs 10nm can be directly compared
  • Wilco1 - Tuesday, April 24, 2018 - link

    The numbers can't be compared literally, they are just labels for the process. However the fabs do use labels that are in the right order, so 7nm is better/smaller/faster than 10nm which again is better than 14nm etc, just like you'd expect.
  • qap - Wednesday, April 25, 2018 - link

    but that only applies within single fab. You can not directly compare processess by using their names between manufacturers.
  • Wilco1 - Wednesday, April 25, 2018 - link

    Well you can to some extent, for example TSMC 16nm is less dense than Intel 14nm, while TSMC and Samsung 10nm are significantly more dense. So calling those nodes 10nm is accurate.

    TSMC 12nm is badly named as it is as dense as the other 14nm nodes.
  • psychobriggsy - Wednesday, April 25, 2018 - link

    Note however that Intel use 1D routing rules on their 14nm, but SS/GF/TSMC provide 2D routing rules, so whilst the basic transistor density is higher on Intel, the achieved overall density isn't as different. This isn't the only example. However seeing as Intel got there so many years ahead of the others I don't think it's worth an argument. The issue is Intel's 10nm process progress, or lack of, right now.
  • Sahrin - Tuesday, April 24, 2018 - link

    This isn't a 1:1 comparison; Intel still leads in some metrics and is also building its process with a different (potentially more complicated) design in mind.
  • teldar - Tuesday, April 24, 2018 - link

    I'm by no means a fab expert. Quite the opposite. But I've read that, I believe, the gates in Intel's process are much more advanced than the gates in everyone else's. The transistors may be similar, but the overall density does not correlate because everyone else is behind in other portions of the manufacturing.

    This may/may not be correct as my understanding may have been faulty and other fabs may have passed Intel in gate manufacturing by now as well. I don't konw. But I have read that Intel still was more dense overall at 14 than other manufacturers' 10.
  • Wilco1 - Tuesday, April 24, 2018 - link

    No your understanding is incorrect, and the opposite is true. TSMC 10nm is significantly more dense than Intel 14nm when you compare raw transistor density (see my link above).

    In real designs it's even worse. TSMC 20nm chips were found to have a higher density than Intel 14nm chips. This is due to Intel prioritizing performance over density (for example Intel's 14+/++ processes are faster but less dense than the original 14nm process - on the other hand TSMC's 12nm process is both faster and more dense than the original 16nm process on which it is based).
  • Dragonstongue - Tuesday, April 24, 2018 - link

    Intel has upped their gate pitch for current 8xxx generation to keep the clock speeds up, but the transistor density is only one part of the "design" Sram (L1-L2-L3 whatever) is also a very distinct Intel has had a historical advantage over other fabs, so they may not have as much density per mm2 now, but, they may still have the raw advantage when all metrics of the die is taken into account.

    lost a bit here gain a great deal more there type deal.

    I think possibly Intels choice to stick with BULK vs SOI or whatever definitely has some advantages (which has been proven) but the smaller the nm design becomes there will be even more shift of what is possible vs what will no longer be to keep the shrinking happen (least this is what I have read)

    AMD stuck with SOI whereas Intel used the "other" this allowed Intel to keep getting ahead year after year where AMD (and others) were stuck with a very low pace of shrinks happening, whereas now it seems that Intel has almost run into a wall because their choice to stick with what they were using becomes ever more complicated if they want to keep density, switching speed, latency etc etc as nice as they can (however you want to word that)

    First to the gate does not mean you will always be the leader, last to the pass does not always mean you cannot win the race either.

    Seems AMD decision to keep at it instead of folding their operations has borne much fruit even if it has taken longer to harvest it.

    the future will be in many many many cores not simple fast ones, like our brain, it relies on insane multi threading much more so than raw mach 20 speeds (for lack of a better explanation) I believe the "old guard" that is Intel and Ngreedia are starting to notice this more and more and AMD is best to keep at it, "mining" and the way they have chosen to build their products is very much starting to come into its own, even if the average person is not using/able to tap into the potential horsepower that is there of course.
  • ZolaIII - Wednesday, April 25, 2018 - link

    Most part I agree with you at least in the first part of the post. The FinFET structure time is at the end & new one's are in late commercial phase of development in order to replace it (gate all around).
    FinFET never whose suitable for analogue in the first place so we got stuck on that field for a long time (with what's considered as the planar bulk today & seen it's last half & full node's years ago), FD-SOI is addressing that now.
    Our brain is not a core nor many core's, it's adaptable neutral structure so future doesn't belong to many core nor high parallel systems it belongs to high adaptable one's or better say it belongs to FPGA's. FPGA can be programmed to become what ever suits the best task that needs to be executed. Potential is almost limitless or better say it's limited the same way as we are limited to use our brains but at least the FPGA program library is permanent and can be more perfected true time which is something we can't do regarding the way we use our brain (as we also forget true time and it degrees after certain time & it stays individual to the end)...

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