Core to Core to Core: Design Trade Offs

AMD’s approach to these big processors is to take a small repeating unit, such as the 4-core complex or 8-core silicon die (which has two complexes on it), and put several on a package to get the required number of cores and threads. The upside of this is that there are a lot of replicated units, such as memory channels and PCIe lanes. The downside is how cores and memory have to talk to each other.

In a standard monolithic (single) silicon design, each core is on an internal interconnect to the memory controller and can hop out to main memory with a low latency. The speed between the cores and the memory controller is usually low, and the routing mechanism (a ring or a mesh) can determine bandwidth or latency or scalability, and the final performance is usually a trade-off.

In a multiple silicon design, where each die has access to specific memory locally but also has access to other memory via a jump, we then come across a non-uniform memory architecture, known in the business as a NUMA design. Performance can be limited by this abnormal memory delay, and software has to be ‘NUMA-aware’ in order to maximize both the latency and the bandwidth. The extra jumps between silicon and memory controllers also burn some power.

We saw this before with the first generation Threadripper: having two active silicon dies on the package meant that there was a hop if the data required was in the memory attached to the other silicon. With the second generation Threadripper, it gets a lot more complex.

On the left is the 1950X/2950X design, with two active silicon dies. Each die has direct access to 32 PCIe lanes and two memory channels each, which when combined gives 60/64 PCIe lanes and four memory channels. The cores that have direct access to the memory/PCIe connected to the die are faster than going off-die.

For the 2990WX and 2970WX, the two ‘inactive’ dies are now enabled, but do not have extra access to memory or PCIe. For these cores, there is no ‘local’ memory or connectivity: every access to main memory requires an extra hop. There is also extra die-to-die interconnects using AMD’s Infinity Fabric (IF), which consumes power.

The reason that these extra cores do not have direct access is down to the platform: the TR4 platform for the Threadripper processors is set at quad-channel memory and 60 PCIe lanes. If the other two dies had their memory and PCIe enabled, it would require new motherboards and memory arrangements.

Users might ask, well can we not change it so each silicon die has one memory channel, and one set of 16 PCIe lanes? The answer is that yes, this change could occur. However the platform is somewhat locked in how the pins and traces are managed on the socket and motherboards. The firmware is expecting two memory channels per die, and also for electrical and power reasons, the current motherboards on the market are not set up in this way. This is going to be an important point when get into the performance in the review, so keep this in mind.

It is worth noting that this new second generation of Threadripper and AMD’s server platform, EPYC, are cousins. They are both built from the same package layout and socket, but EPYC has all the memory channels (eight) and all the PCIe lanes (128) enabled:

Where Threadripper 2 falls down on having some cores without direct access to memory, EPYC has direct memory available everywhere. This has the downside of requiring more power, but it offers a more homogenous core-to-core traffic layout.

Going back to Threadripper 2, it is important to understand how the chip is going to be loaded. We confirmed this with AMD, but for the most part the scheduler will load up the cores that are directly attached to memory first, before using the other cores. What happens is that each core has a priority weighting, based on performance, thermals, and power – the ones closest to memory get a higher priority, however as those fill up, the cores nearby get demoted due to thermal inefficiencies. This means that while the CPU will likely fill up the cores close to memory first, it will not be a simple case of filling up all of those cores first – the system may get to 12-14 cores loaded before going out to the two new bits of silicon.

The AMD Threadripper 2990WX 32-Core and 2950X 16-Core Review Precision Boost 2, Precision Boost Overdrive, and StoreMI
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  • Lolimaster - Monday, August 13, 2018 - link

    Then build one yourself.
  • tmnvnbl - Monday, August 13, 2018 - link

    How did you measure power numbers for core/uncore? Did these validate with e.g. wall measurements? The interconnect power study is very interesting, but I would like to see some more methodology there.
  • seafellow - Monday, August 13, 2018 - link

    I second the was measurement performed? How can we (the readers) have confidence in the numbers without an understanding of how the numbers were generated?
  • GreenReaper - Wednesday, August 15, 2018 - link

    Modern CPUs measure this themselves. AMD itself has boasted of the number of points at which they measure power usage throughout its new CPUs. Check out 'turbostat' in the 'linux-cpupower' package - or grab a copy of HWiNFO that will show it.
  • Darty Sinchez - Monday, August 13, 2018 - link

    This here article be awesome. I is so ready to buy. But, me no have enough money so I wait for it sale.
  • perfmad - Monday, August 13, 2018 - link

    So is the 2990WX bottlenecking in Handbrake because of the indirect memory access for some cores? Would be interesting to know if that bottleneck can be worked around by running multiple encodes simultaniously, The latest Vidcoder beta uses the handbrake core and has recently added support for multiple simultanous encodes. Would be really appreciated if you had time to look into that.

    Also do you share the source file and presets you use for the handbrake tests so we can run them on our hardware to get a comparison? My CPU isn't one you've tested.

    Thanks for the review thus far.
  • AlexDaum - Monday, August 13, 2018 - link

    I think, the problem with the memory bandwidth cannot be easily fixed, as it isn't a Problem, that one Process uses to much memory, but one core on one of the dies without memory controller, needs to access the infinity fabric to get Data. When all of the cores are active and want to fetch data from memory, it would cause contention on the IF Bus, which reduces the available memory bandwidth a whole lot and the core is just waiting for memory.
    This is just my speculation though, not based on facts, other than the bottleneck.
  • Aephe - Monday, August 13, 2018 - link

    Those 2990WX Corona results! Can't wait to get a machine based on this baby! Holding up for TR2 release was worth it for me at least.
  • Ian Cutress - Monday, August 13, 2018 - link

    That benchmark result broke my graphing engine ! Had to start reporting it the millions.
  • melgross - Monday, August 13, 2018 - link

    It’s interesting. This reminds me of Bulldozer, where they made a bad bet with floating point (among some other things), and that held then back for years. This looks almost too specialized for most uses.

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