Intel Goes For 48-Cores: Cascade-AP with Multi-Chip Package Coming Soonby Ian Cutress on November 5, 2018 2:00 AM EST
- Posted in
- Enterprise CPUs
- Xeon Scalable
- Cascade Lake
Ahead of the annual Supercomputing 2018 conference next week, Intel is today announcing part of its upcoming Cascade Lake strategy. Following on from its server-focused Xeon Scalable Skylake family, Intel has already pre-announced that Cascade Lake-SP will form the next generation, with a focus on compute and security. Today’s announcement is for a product family to run alongside Cascade Lake-SP, called Cascade Lake-AP, or Cascade-AP for short. Cascade-AP is going to be aimed at ‘advanced performance’. In order to implement this new processor family, Intel is combining multiple chips in the same package.
Scaling up to 48-Cores Per CPU
Intel is still keeping a lot of details for Cascade-AP under wraps for now, but what we do know is some high level specifications: Cascade-AP processors will be up to 48 cores, possibly with hyperthreading, and is aimed at dual socket servers, for a total of 96 cores in a 2S system. As a result, a single Cascade-AP is essentially a 2S Xeon setup on a single chip.
Each Cascade-AP processor will have 12 DDR4 DRAM channels, although maximum capacity of memory has not been announced. Connection between the processors will be the standard UPI connection as seen on current Xeon Scalable processors, although connection speed was not specified. It would appear that Cascade-AP is not designed to scale beyond a 2S system.
Each Cascade-AP lake processor will offer up to 48 cores, and in order to do this Intel is using a multi-chip package (MCP). At this point we believe that Intel is using two silicon dies in the package, specifically two ‘XCC’ dies which should be 28-core by design but will be only enabled up to 24-core per silicon die. Intel did confirm that these dies are connected by UPI over the package, and not with Intel’s EMIB technology. This is unfortunate, given how Intel has promoted its EMIB technology as an alternative to interposers, but we have yet to see it in a product that connects two high-powered chips together, as was originally envisioned when the technology was first announced. It does mean however that it can use the same silicon as will be found in the standard Xeon Scalable processors.
No information was given about TDP per processor, or pricing, PCIe lanes, memory capacity/support, frequencies, or variants. We were told that it will be launched at the same time as the full Cascade Lake family ‘in the first part of 2019’ (to directly quote). Intel did give some base performance numbers, suggesting that a processor scores 3.4x higher than an EPYC 7601 on Linpack and 1.3x higher on Stream Triad. Deep Learning inference, a major workload for these new parts, was quoted as scoring 17x the base Skylake-SP launch performance, which would be 1.55x the original quoted Cascade-SP launch performance with the new VNNI instructions.
Given the extra power requirements and extra memory requirements, we fully expect Intel to be using a new socket for this processor. Rather than LGA4367, with 4367-pins, there have been recent leaks suggesting that an LGA5903 socket be where Cascade-AP will end up, although Intel has not confirmed this. Intel did state that Cascade-AP will be shipping for revenue in Q3 2018 to its high-profile customers as part of its early access program, however widespread availability will be ‘in the first part of 2019’.
More Cores Per Socket, But Potentially a Worse 4S System
With this new type of processor, even given Intel’s previous competitive analysis of MCP designs, Intel is pushing up the number of cores per socket, and cores per 2S system. The 2S server market is one of Intel’s biggest across the whole company, and the idea is to offer more value. It’s hard to state the impact that Cascade-AP will have on the product portfolio, but it comes to mind that Intel is trying to condense a 4P system into a 2P system, though it probably won’t perform as well.
Take, for example, a 24-core 4P system, which has 96 cores total. Using Intel’s 3 UPI links, the communication between the four processors allows each processor to talk to each other processor in only one hop. Each processor has six channels of memory, access to 48 PCIe lanes, potential access to OmniPath, etc.
In a Cascade-AP two socket system, it all depends on how the links between the sockets are formed.
We already know that within a single package, the two silicon dies will talk to each other over UPI through the package. This is lower power than a socket-to-socket UPI link, and might take advantage of lower latency as well. That is all well and good.
But between the sockets is where questions will lie. If Intel is only using one UPI link between the sockets, then only one die from each socket will be connected. This is essentially a straight chain connectivity, meaning that to talk to a silicon die on the other socket, it may require two hops.
If Intel is using two UPI links between the sockets, then we have a situation similar to a Xeon Gold-2UPI system where the processors are arranged in a square and there is no cross-connection. This creates a communication imbalance between processors and memory which might be hard to predict unless the software can enumerate and deal with it effectively.
The other option is if Intel is using four UPI links between the sockets – two from each silicon die, to one each of the other silicon dies on the other processor. This is identical to a 4P 3UPI system, except that the dual socket configuration makes this all the more complex. It would require at least two UPI links to cross over each other with the traces on the motherboard. This either requires a thick motherboard (adds cost) or a control repeater chip that can do it easier. But even then, we’re dealing with a non-uniform memory architecture in each socket and between sockets with different latencies between the hops. At least in a natural 4S system, the arrangement can ensure latencies are equal.
There’s also the question of PCIe lanes. Intel has not given a number, but we suspect it to be anywhere between 48 (24 per die) or 96 (48 per die) per socket. Which would be identical to a 4S system again.
Further to that, a question of frequencies. A current 24-core Xeon Platinum runs at 205W. Intel is not going to put the TDP at 410W when it puts two together – it will have to lower the frequency to hit something more suitable for the large socket. Add into that the complexity of supplying 48 cores with enough power to be competitive. With separate chips, each socket can have higher frequencies.
The only saving grace here would be actual physical volume. Some datacenters are all about compute density, and for some providers looking to deploy mass x86 CPUs in their offering, this could be a winner with them. Intel has repeatedly cited that Xeon-based inference as a major source of customers, hence the inclusion of features like VNNI on Cascade Lake to help drive that market.
Timeline for Cascade Lake and Cascade Lake-AP
Intel stated that they are shipping processors for revenue to select customers as part of its early adopter program. The new parts will be launched in the first part of 2019, with the full Cascade Lake family (SP and AP) being launched at the same time. We asked a series of pertinent questions after our briefing, however Intel was unwilling to answer anything additional to our presentation. Some further information (or demonstrations) might be seen at the Supercomputing 2018 conference happening next week.
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The Benjamins - Wednesday, November 7, 2018 - linkRome has now been announced to be available this year with 64c128t
Martin_Schou - Tuesday, November 6, 2018 - linkHey, look at that - AMD has announced 64 core Rome the very next day. So now Intel's newest architecture really IS behind by 16 cores. Oh, and it has PCIe 4.0 support out of the box.
The Benjamins - Wednesday, November 7, 2018 - linkIntel only made this as a stop gap, but their 48c part is going to need a socket 50% bigger then Rome. does not look good for intel.
HStewart - Monday, November 5, 2018 - linkIntel has been connecting dies together in a package since the days o Pentium D and just because they did today - one calls this infringe on patents from AMD and also glue, if that was truly the case then AMD has infringe on Intel patents
One thing I am deeply concern on these patents - if an Intel person says anything about AMD product - they get viciously attack - but then they is article like this where Intel has done something and it get polluted with discussion about AMD.
I have the right to like Intel, and so does users that like AMD, but would success some maturity in the forums and keep this Intel vs AMD stuff out of logical discussions.
sa666666 - Monday, November 5, 2018 - linkThis is rich; the resident Intel fanboi extraordinaire complaining about fanboyism. You're the one that constantly brings mention of Intel into AMD articles, as you just can't resist when Intel is being cast in a bad light. And now you want people to stop talking about AMD in an Intel article?
Try looking in the mirror and analyzing your own behaviour before you denounce it in others. And to be clear, it's not Intel favouritism from you that is annoying, it's the complete illogic of some of your statements. If you would just preface all your articles with "I am an Intel supporter, always will be, and don't accept that they can do any wrong", then maybe some of your comments would be more palatable. At least you'd be honestly sticking to your opinion without the passive-aggressive attitude.
Talk about the pot calling the kettle black ...
HStewart - Monday, November 5, 2018 - linkI only mention Intel in AMD articles if some one else blabs it out.
I don't consider myself Intel Fanboy - I have other products include from AMD - I just prefer Intel, it seems that some uses are AMD Fanboy's - they are consider Intel Fanboy.
I honest did try to give AMD a test with my Dell XPS 15 2in1.
I would take a look in the mirror from AMD statements - at least Anandtech is not as bas WCCFTech or ExtremeTech which are bluntly AMD bias places.
I wrote this message, because I don't like Intel related article that keep pushing AMD stuff - if this was done on AMD article - one would be harass like no tomorrow. Only because of long history of techy geekness that I even care about forums.
But lets be honest, the average consume does not care if Intel has dual connect 24 Cores and AMD core is 32 core ( actually 8 connect 4 cores ) they want something to emails and spreadsheets.
Which to some people might be iPad or Samsung Tab Sx tablet - which is actually Intel and AMD's bigger threat.
PeachNCream - Monday, November 5, 2018 - link"I don't consider myself Intel Fanboy"
Everyone else does.
HStewart - Monday, November 5, 2018 - linkOf course AMD fanboy's believe that - if not AMD you must be Intel Fanboy.
I just have 30 years experience developing on Intel machines and trust them
PeachNCream - Tuesday, November 6, 2018 - linkBeing a code monkey for the part 30 years hasn't helped your communication skills in the slightest. Beyond that, if you really think that everyone who believes you're an slobbering Intel shill _must_ be diametrically opposed to you and a slobbering AMD shill yet somehow refuse to also acknowledge your blind loyalty, then I'm glad I've never hired you to bang out code for any project I've led because you're truly lost in the sauce.
PeachNCream - Tuesday, November 6, 2018 - linkYikes, your awful English is rubbing off on me. "Being a code monkey for 30 years hasn't helped your communication skills in the slightest."
Sheesh, I need a time machine to hop over to Anandtech of the future where we get edit capabilities. Hmm...I guess I'll set the time machine's dial to 1998. That sounds like a reasonable year to expect an edit button.