Micron Shipping LPDDR5 DRAM
by Billy Tallis on February 6, 2020 8:30 AM ESTMicron has announced their first LPDDR5 DRAM is in mass production and now shipping to customers. The new RAM is significantly faster and more power efficient than LPDDR4x. One of the first products to use the new LPDDR5 will be the upcoming Xiaomi Mi 10 smartphone.
Micron's LPDDR5 is available in 6GB, 8GB and 12GB packages, with speeds of 5.5Gbps and 6.4Gbps per pin. The faster speed grade is a 50% improvement over their fastest LPDDR4x products (4266Mbps per pin), and Micron also claims better than 20% reduction in power use compared to LPDDR4x. Micron will also soon be offering multi-chip packages pairing LPDDR5 with UFS-based flash storage; these products will be available sometime during the first half of the year.
The most visible applications for LPDDR5 will be this year's crop of flagship smartphones, but Micron is also targeting automotive and networking applications with the obligatory references to 5G and AI driving demand for faster memory.
Related Reading:
- Micron’s DRAM Update: More Capacity, Four More 10nm-Class Nodes, EUV, 64 GB DIMMs
- Samsung Starts Production of LPDDR5-5500 Devices: 12 GB of DRAM in a Smartphone
- Samsung Announces First LPDDR5 DRAM Chip, Targets 6.4Gbps Data Rates & 30% Reduced Power
- Samsung Starts Production of 16 Gb LPDDR4X Chips Using 2nd Gen 10nm Tech
- Micron Kicks Off Mass Production of 12 Gb LPDDR4X DRAM Chips
33 Comments
View All Comments
Billy Tallis - Thursday, February 6, 2020 - link
6-12GBytes are the capacities of the multi-chip packages. Per-die capacities haven't been announced but are likely 12Gbit and 16Gbit.MarionGrandJ - Wednesday, February 12, 2020 - link
This sentence is poorly worded "Micron will also soon be offering multi-chip packages pairing LPDDR5 with UFS-based flash storage; these products will be available sometime during the first half of the year." It seems to be Micron own words. The true meaning is: Micron will be offering a storage subsystem to be soldered that'll include an UFS controler, and a stacked NAND die and LPDDR5 DRAM cache die.Billy Tallis - Monday, June 29, 2020 - link
Not cache. They actually put flash and DRAM both in the same package to both be used by the host SoC.