FMS 2014: Marvell Announces NVMe-Enabled PCIe 3.0 x4 88SS1093 SSD Controller
by Kristian Vättö on August 21, 2014 12:10 PM ESTTwo weeks ago Marvell announced their first PCIe SSD controller with NVMe support, named as 88SS1093. It supports PCIe 3.0 x4 interface with up to 4GB/s of bandwidth between the controller and the host, although Marvell has yet to announce any actual performance specs. While PCIe 3.0 x4 is in theory capable of delivering 4GB/s, in our experience the efficiency of PCIe has been about 80%, so in reality I would expect peak sequential performance of around 3GB/s. No word on the channel count of the controller, but if history provides any guidance the 88SS1093 should feature eight NAND channels similar to its SATA siblings. Silicon wise the controller is built on a 28nm CMOS process and features three CPU cores.
The 88SS1093 has support for 15nm MLC and TLC and 3D NAND, although I fully expect it to be compatible with Micron's and SK Hynix' 16nm NAND as well (i.e. 15nm TLC is just the smallest it can go). TLC support is enabled by the use of LDPC error-correction, which is part of Marvell's third generation NANDEdge technology. Capacities of up to 2TB are supported and the controller fits in both 2.5" and M.2 designs thanks to its small package size and thermal optimization (or should I say throttling).
The 88SS1093 is currently sampling to Marvell's key customers and product availability is in 2015. Given how well Intel's SSD DC P3700 fared in our tests, I am excited to see more NVMe designs popping up. Marvell has known to be the go-to controller source for many of the major SSD manufacturers (SanDisk and Micron/Crucial to name a couple), so the 88SS1093 will play an important part in bringing NVMe to the client market.
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Peeping Tom - Thursday, August 21, 2014 - link
More innovation, please.chris81 - Friday, August 22, 2014 - link
Always keep in mind that SATA is half-duplex, but PCIe is full-duplex. So even PCIe 2.0 x2 with 10 Gb/s is much better than 6 Gb/s SATA III (both use 8b/10b encoding)FaaR - Friday, August 22, 2014 - link
It shouldn't be half duplex - well in theory anyway - due to having separate wires for send and receive...