With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a lithography machine – that is, chips bigger than the maximum size that a single chip can be produced. We've already seen efforts such as Cerebras' truly massive 1.2 trillion transistor wafer scale engine, and they aren't alone. As it turns out, TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they've announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.

Overall, the proposed 1,700 mm² interposer is twice the size of TSMC's 858 mm² reticle limit. Of course, TSMC can't actually produce a single interposer this large all in one shot – that's what the reticle limit is all about – so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.

The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC's EUV-based 5 nm (N5) process technology. This system-in-package product features ‘multiple’ SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom's press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung’s latest HBM2E chips can offer.

By doubling the size of SiPs using its mask stitching technology, TSMC and its partners can throw in a significantly higher number of transistors at compute-intensive workloads. This is particularly important for HPC and AI applications that are developing very fast these days. It is noteworthy that TSMC will continue refining its CoWoS technology, so expect SIPs larger than 1,700 mm2 going forward.

Greg Dix, vice president of engineering for the ASIC products division at Broadcom, said the following:

"Broadcom is happy to have collaborated with TSMC on advancing the CoWoS platform to address a host of design challenges at 7nm and beyond. Together, we are driving innovation with unprecedented compute, I/O and memory integration and paving the way for new and emerging applications including AI, Machine Learning, and 5G Networking."

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Source: TSMC

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  • azfacea - Wednesday, March 4, 2020 - link

    lol Broadcom. what the hell do they need this for ? TSMC I totally get.
  • Billy Tallis - Thursday, March 5, 2020 - link

    High-speed switch ASICs push the reticle size limit. See eg. http://web.stanford.edu/class/cs349f/slides/Stanfo... Chiplets can be used to eg. separate the switch core from the PHYs. Two years ago I saw Marvell demo a 12.8 Tb/s switch chip that was 600+ mm^2 for the central chip and ~65mm^2 for each of 8 chiplets around it, for a total of over 1100 mm^2 of silicon—all for about half the bandwidth Broadcom is talking about.

    Now imagine wanting to put some compute capabilities and HBM on the same package instead of it being just an Ethernet switch.
  • azfacea - Thursday, March 5, 2020 - link

    ok that make sense. i was just trying to have some fun with broadcom. lol
  • yeeeeman - Thursday, March 5, 2020 - link

    Broadcom has one of the best networking chip. And also one of the biggest.
  • brucethemoose - Wednesday, March 4, 2020 - link

    So... a huuge AI accelerator?

    Heck, maybe Broadcomm is making a fully self contained AI package, with a ARM SoC and a shared IO die? That would actually be pretty neat, as (with the right interconnect) they could shove a ton of those suckers into a single rack, without having to make space for x86 CPUs and DIMMs.
  • Whiteknight2020 - Thursday, March 5, 2020 - link

    Edge inference/training more likely.
  • Valantar - Thursday, March 5, 2020 - link

    What node is the interposer being made on?
  • eek2121 - Thursday, March 5, 2020 - link

    So, I have heard from a couple different parties that the reticule limit for TSMC 7nm is roughly half that of the previous 858mm2. Can anyone with actual knowledge of this provide some insight?
  • name99 - Thursday, March 5, 2020 - link

    No. BUT there are interesting things coming...

    OK, here's my understanding. I think it's essentially correct, though anyone feel free to correct details.

    So the way the industry operates today is everything is standardized around a mask size (for a single die) of 104mm x 132mm. This fits inside a standardized length (what's been termed the 6" reticle) of 6"= 152mm, with some extra stuff on the side for alignment markers and suchlike.
    The mask image, in turn, is shrunk down by 4x to make an image 26mm x33mm=858mm^2 which is the maximum size of chip you can manufacture. That's where we are today, for 193µm and EUV lithography, so both 7 and 5nm.

    What about going forward?
    The problem is that as you go to finer features on the mask, the 3D geometry of the mask (ie the fact that some parts are slightly higher than other parts, because that's how you made the mask in the first place, by cutting away or depositing) starts to matter. Rays that come in from an angle, as opposed to from directly above the mask, cast shadows that are large on same parts of the mask, weak in other parts, depending on the precise relationship between the line location and the illumination pattern. Net effect is that some lines are effectively wider than other lines.

    Right now this is under control through things like a careful illumination pattern. But it becomes unacceptable as you go to higher NA, which is required to get to enhance resolution.

    So: high resolution needs high NA which means 3D mask effects destroy your higher resolution :-(
    What to do?
    The only option that seems to be feasible is to change the reduction ratio (that shrinking of the mask size by 4x down to the die size). If this is increased (to 5x, 6x, even 8x) then the geometry of the rays reflecting off the mask can be adjusted to avoid the 3D oblique shadowing problems for another generation or two. BUT
    if you have been following along, you'll realize that a reduction of 6x rather than 4x implies a die size now of 17.3mm x 22mm, basically half the current maximum die area. Oops...
    Still fine for mobile, even desktop, chips, problematic for the monster sized chips...

    So how do we deal with THIS problem?
    Options are
    - go to larger reticles, say 9". Maybe one day that will happen. But everyone wants to avoid that as long as possible because it affects everything mask-related, like the mask generation tools, the test tools, even the basic transport tools for moving them around.
    - new types of masks with less 3D effects. Well people have been trying for years. No luck so far.
    - accept a smaller "die" and then join them somehow. The joining could be like Cerebras (so manufactured on the wafer between the individual die's) or created after the fact (ie chiplets, like the technology in the article)

    So currently the max die size remains about 858mm^2, but this is expected to shrink (unless something unexpected happens) as EUV is required to move to smaller NA (which I guess starts at 3nm?)
    Basically the larger picture, IMHO, is you should read this the same way you should read the Cerebras stuff. Very smart TSMC, always killing two birds with one stone, is simultaneously providing what one or two customers want today but ALSO (just as a plan B) doing the R&D for what more and more customers may require in the future if high-NA EUV does require smaller maximum die area's.
  • FullmetalTitan - Saturday, March 7, 2020 - link

    For the high NA (0.55) Twinscan 3400C in development by ASML, the planned field size shrinks from 26mm x 33mm to 26mm x 16.5mm. The magnification changes from 4x/4x in the x/y directions to 4x/8x.
    There are some interesting computational design techniques that allow for reduction of those shadowing effects, but there are some hard tradeoffs being made to move to high NA EUV.

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