During the opening keynote at Intel's Innovation event in San Jose, Chief Executive Officer Pat Gelsinger unveiled a score of details about the upcoming Meteor Lake client platform. Intel's Meteor Lake marks the beginning of a new era for the chipmaker, as they move away from the chaotic Intel 7 node and go into a rollout of their Foveros 3D packaging with EUV lithography for their upcoming client mobile platform. Meteor Lake uses a tiled, disaggregated chiplet architecture for its client-centric processors for the first time, changing the very nature of Intel's consumer chips going forward. And, according to Intel, all of these changes have allowed them to bring some significant advancements to the mobile market.

Intel's first chiplet-based consumer CPU breaks up the common functions of a modern CPU into four individual tiles: compute, graphics, SoC, and an I/O tile. Within the makeup of the compute tile is a new pair of cores, a P-core named Redwood Cove and a new E-core called Crestmont. Both these cores promise IPC gains over their previous counterparts, but perhaps the most interesting inclusion is a new type of E-core embedded directly into the SoC tile, which Intel calls 'Low Power Island.' These new LP E-cores are designed with the idea that light workloads and processes can be taken off the more power-hungry compute tile and offloaded onto a more efficient and lower-powered tile altogether. Other major additions include a first-for-Intel Neural Processing Unit (NPU), which sits within the SoC tile and is designed to bring on-chip AI capabilities for workloads and inferencing, paving the way for the future.

With Meteor Lake, Intel is aiming to put themselves in a more competitive position within the mobile market, with notable improvements to compute core hierarchy, Intel's Xe-LPG Arc-based graphics tile looking to bolster integrated graphics capabilities, and an NPU that adds various AI advantages. Meteor Lake also sets the scene for Intel and modular disaggregation, with Foveros 3D packaging set to become a mainstay of Intel's processor roadmap for the future, with the Intel 4 process making its debut and acting as a stepping stone to what will become Intel's next mainstay node throughout its fabs, Intel 3.

Intel Meteor Lake: Intel 4 Using Foveros 3D Packaging

Intel's Meteor Lake architecture is not just another iteration in the long line of processor advancements; according to the company it's a revolutionary leap forward. Eloquently put by the executive VP and GM of Intel's Client Computing Group (CCG), Michelle Johnston Holhaus, at Intel's Tech Tour 2023 in Penang, Malaysia, she remarked that Intel had reached an inflection point in their client roadmap. Unveiling more details about Meteor Lake at the Intel Technology Tour in Malaysia, the architecture is an advancement from its current client processors regarding performance as we advance through Intel's '5 nodes in 4 years' roadmap.

Meteor Lake is built upon Intel's disaggregated architecture pushed through by Foveros packaging. This is designed to optimize both performance and energy efficiency. The architecture itself consists of four unique and distinct tiles connected via Intel's Foveros 3D packaging technology. This includes the compute tile, which is built on Intel 4, while the graphics tile is built on TSMC's N5 node. The other two tiles Intel implements within Meteor Lake are the SoC tile which acts as the central hub through the embedded NOC. This is the first time Intel has used a Network-on-Chip (NOC) on their client processors, which is a simplified approach to the NOC on their existing Agilex FPGAs. While on Agilex, the NOC is individualized into different NoC targets and switches within the substructure of the NoC, on Meteor Lake, it directly connects to the I/O fabric through the IoC, which then goes into the I/O fabric. The NOC itself is directly connected to the graphics tile, compute tile, and other components within the SoC.

This modular approach allows for a ground-up and scalable power management architecture that supports disaggregation, enabling each tile to function independently. This disaggregated design prioritizes performance by negating bandwidth bottlenecking through things like the I/O on a monolithic design and targets enhanced power efficiency. Perhaps the most notable element of disaggregation is that Intel can select specific silicon processes for each tile and isn't limited to one process node. On top of the power efficiency and package area benefits of a tiled architecture, it is cheaper for Intel to manufacture CPUs with fewer masks through EUV, but it allows Intel to scale out new IP into future products while keeping the same base, which is another cost-saving factor (for Intel).

Compared to mobile Raptor Lake, which was done using Multi-Chip Packaging (MCP), Meteor Lake uses Foveros BGA packaging and offers low-power die-to-die interconnects, which Intel confirmed has a small power penalty of between 0.15 and 0.3 picojoules (pJ) communicating from tile to tile. Some of the advantages of Foveros include better customizability through tiling, which allows Intel to manufacture chips and implement specific tiles and IP depending on the grade of the chip, etc., low power with more I/O, or high-end tiles with all the latest gadgets and gizmos. With the Intel 7 node not being as viable as they would have hoped, Intel promises higher wafer yield on Intel 4, which uses less wafer space for logic-based silicon.

Power management is done using a scalable power management system that supports the independent functioning of each tile. Coordination between multiple power management controllers (PMC) and system software is designed to be optimized for various workloads. Intel's Meteor Lake architecture also introduces a new scalable fabric to improve energy efficiency and extend bandwidth in areas that have been previously bottlenecked, such as I/O.

Touching more on the power controllers within the Meteor Lake architecture, Intel has integrated independent Power Management Controllers within each of the tiles. As part of the disaggregation of using Foveros, each tile needs to be independently power managed, and using PMCs on the NOC, the I/O fabric, as well as each tile allows power management to be agnostic depending on the number of the cores on each package.

Meteor Lake itself represents a monumental architectural shift, not just a mere incremental update, as it represents the most significant architectural transformation in client processors in four decades. This is because it's the first client processor to be made using chiplets instead of a monolithic design. The architecture is designed to be the cornerstone of Intel's strategy to push PC innovation for the next decade. Looking at some of the finer details of Intel's Meteor Lake architecture, it uses Intel's Foveros packaging technology, which uses 3D chip stacking to tackle the pitfalls of traditional 2D chip layouts.

As we can see from the above disclosure from Intel at Hot Chips 2023, the top and bottom layers have bumps for interconnecting each die together. Using the Foveros FDI packaging offers a low-voltage complementary metal oxide semiconductor (CMOS) interface, which means the power circuitry can be run with lower voltages and, thus, with a lower power envelope. Another benefit of FDI is both synchronous and asynchronous signaling, which means signal transmission can handle fully duplexed data blocks.

Constructing a Meteor Lake SoC includes a package substrate, which is the foundation for the base tile to sit onto, which uses the Foveros Die Interconnect (FDI). The base tile has a 36µm die to die pitch with metal layering and a 0.15 to 0.3 pJ operating power at 2 GHz; this may fluctuate or vary depending on voltages, amps, and frequency. As it's a base tile that isn't an active chiplet itself, its only function is to serve as a base for all of the various logic, and metal layers for the chiplets to be placed upon.

The makeup of Intel's Meteor Lake architecture uses four distinct tiles to create a Meteor Lake CPU. This includes a Compute, SoC, GPU, and an I/O tile, all with distinct uses, capabilities, and flexibility in regard to IP. Power management also gets a revamp. With disaggregation through Intel's Foveros packaging technology, each tile in Meteor Lake requires its own power management. Intel's solution is a hierarchical power management system that uses Power Management Controllers on the NoC, IO fabric, and each individual tile.

Over the next few pages, we'll give an insight into each of the four tiles, what each tile brings to the table, and more about the various technologies driving innovation through Meteor Lake.

Compute Tile: New P and E-Cores on Intel 4
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  • kwohlt - Tuesday, September 19, 2023 - link

    The market for people who find TB4 to be insufficient is too small to delay MTL for them
  • Exotica - Wednesday, September 20, 2023 - link

    Source or market research please ? I have the feeling that many enthusiasts will not be interested. Because of missing TB5. And also because of its ipc improvements (or lack thereof) vs raptor lake.

    Meteor lake certainly is impressive. But it seems to be less about raw performance and more about the process improvement. Foveros. Chiplets. Euv. New manufacturing abilities. AI engine. Power efficiency. Newish gpu.

    But from a generational uplift perspective, from a raw cpu performance to the thunderbolt io, I t’s not much of an upgrade for enthusiasts. Intel should’ve just launched MTL in Dec and then announced TB5 in January. What was the reason to announce TB5 before the MTL reveal?

    I guess we will have to wait on arrow lake mobile (if that’s a thing) or lunar lake for TB5 on laptops.
  • kwohlt - Wednesday, September 20, 2023 - link

    You need Market Research to tell you TB4 bandwidth is sufficient for majority of users? 40Gb/s can drive easily gigabit interent and multiple monitors. Most jobs do not require more. At the Fortune 500 I manage IT for, we still haven't even switched to thunderbolt as 3.1 docks are more than sufficient.

    There's market research on TB4 trends for purchase, that i'm not going to pay for, so we'll just have to settle on "Intel's market research determined that delaying their next gen product line for this 1 feature, potentially causing delays across OEMs 2024 product lines in the process, was not worth it"
  • PeachNCream - Thursday, September 21, 2023 - link

    "...many enthusiasts..."

    While that segment might be outspoken, the percentage of the overall market is tiny and the percentage that cares among that fraction is even smaller. Basement dweller computer nerds and the e-sports people they idolize don't buy the hundreds of thousands of units that a computer manufacturer purchases. Sure, they get a minor head nod from the company to keep them from slobbering and raving about being ignored, but that's done because it's cheap to coddle them with marketing speak and make them believe features are targeted at them so their ego balloons aren't popped and sites like this have a bone or two to throw them once in a while, but ultimately, no one cares what they want as long as they fanboy argue in favor of their preferred brand with other nerds that like the competition.
  • TheinsanegamerN - Thursday, September 21, 2023 - link

    Exactly. TB5 is exciting and meteor lake is mostly DoA without it. Who would invest thousands into a machine that cant make use of newer functionality?
  • KaarlisK - Tuesday, September 19, 2023 - link

    Was this just written by having an AI interpret the slides? And then OCR failed?
    "This means that higher Out-of-Service (OoS) work is allocated to P-cores for more demanding and intensive workloads, while lower Quality-of-Service (QoS) workloads are directed to E-cores, primarily to save power"
  • Ryan Smith - Tuesday, September 19, 2023 - link

    No, it was done by a sleep-deprived human.
  • KaarlisK - Tuesday, September 19, 2023 - link

    Thank you for the explanation.
    The problem is, I caught at least three more mistakes like this, where a wrong assumption is made about what the text on a slide actually means. In which case (knowing that I'm not an expert), how can I be certain that there aren't many more mistakes that I haven't spotted?
    We do come to Anandtech for in-depth analysis, which requires that trust.
  • Ryan Smith - Tuesday, September 19, 2023 - link

    The blunt answer is that we're imperfect (to err is human). We've made mistakes in the past and will continue to do so in the future. But we always own up to those mistakes, and will correct anything if we catch it (or if it gets pointed out).
  • DannyH246 - Tuesday, September 19, 2023 - link

    Wow! Intel have some revolutionary ideas here!! Their chiplet approach will change the industry.
    Would be what i'd have said if they'd have presented this 6 years ago. My response today is...meh.

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