Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors

Our Hygon Systems

8-core Dhyana and Dual 32-core Dhyana Plus

The full range of Hygon’s known releases boils down to two platforms: one containing a single 8-core Zen 1 die, similar to the desktop range of processors (or EPYC 3000), and a set of server processors built from four dies in a similar arrangement to Naples.

The 8-core engineering sample system we have in to test didn’t provide any exact SKU numbering – on the CPU it says ‘C86’ which is meant to imply ‘Chinese x86’. The rest of the numbering is likely linked to the wafer and batch that this silicon came from, however we do not have decoder rings for those. 

The motherboard uses a microATX form factor, and is very much a server motherboard with the DDR4 slots horizontal rather than vertical in order to direct airflow through the system in a server chassis. Starting primarily with the socket, what we have is a non-socketed BGA design, such that this CPU cannot be upgraded because it is bonded to the motherboard, similar to what we see with laptops and embedded systems. The mounting holes are the thing that surprises me here – these are not the AM4 mounting holes that we typically see with the consumer version of Ryzen, but these mounting holes are Intel mounting holes. Someone must have a lot of old Intel coolers around, I guess? Either that or it makes it easier for Hygon’s partners to find specific server grade coolers.

The CPU has a six-phase power delivery system, and as this is a pure CPU product, there is no integrated graphics. There is a form of 2D graphics provided by the IPMI controller in the bottom left, the classic ASPEED AST2500 chip that we commonly see in server systems. Unlike other microATX motherboards, there isn’t the typical four slot design here, but a three slot design, with two full length PCIe 3.0 slots (capable of x16/x0 or x8/x8) and an open ended PCIe x4 slot.

Normally these CPUs don’t really need a chipset because they have some SoC level IO functionality on the silicon, though consumer Ryzen CPUs were paired with X370 chipsets when the Ryzen 1000 family first launched. Instead of using those chipsets, Hygon has paired the CPU with a Lattice Semiconductor FPGA to act as a chipset of sorts. This gives the motherboard an odd set of combined IO, including SATA ports, four dual LED displays, a number of custom connectors and buttons, and a lot of undocumented things we don’t know. For example, there appears to be two batteries on the motherboard – one presumably to keep the onboard time, but the other seems more permanent and is not obvious why it is there.

Here’s the motherboard where we’ve put an equivalent AM4 consumer Ryzen CPU on top, to show the size.

By comparison, the dual socket server is a bit of a beast. As we understand it, these servers were built for both compute and storage, with each CPU paired with four breakout connectors capable of four U.2 drives or 16-way SATA connectivity. The CPUs have eight channel memory capabilities, but due to a couple of reasons we had to test them in quad channel mode.

The CPUs in this case also say C86, but also have the model number 7185 on them, indicating a 32-core CPU. The carry case is red, whereas Naples EPYC CPUs were blue, Threadripper CPUs are orange, and Rome EPYC CPUs are green. The red might be a nod to the Chinese angle for these CPUs, however no-one we spoke to was able to confirm this.

The server is actually a Sugon design, with 12 front panel 2.5-inch drive slots. For the 8-core system, that was put into a standard desktop case and fitted with a CPU cooler. Both systems were tested though remote desktop access, as Wendell was hosting them in his labs in Kentucky while I’m all the way back in London.

When trying to probe the CPUs, CPU-Z didn’t seem to have much of a clue. The software provided this interface on the 8-core consumer, showing a 3.2 GHz frequency, but only one core, and no other details aside from support for AVX, AVX2, and FMA3. For the server CPUs, CPU-Z failed to run at all. What we were able to determine is that the software thought that every core was a separate socket, and it appears that some of the usual ways to access this data on the AMD consumer CPUs have all been changed here for the Hygon models, either to evade detection using usual methods, or to conform to different standards. One interesting note is that while CPU-Z detected AVX and AVX2, some of our software couldn’t, and we had to revert to SSE detection in order to get that software to even run.