Samsung Foundry on Wednesday revealed that it has started mass production of SoC products using its second generation 10 nm Low Power Plus (10LPP) fabrication technology. The new manufacturing process will enable developers of chips to reduce power consumption or increase performance of their products compared to the first-gen 10 nm tech (10LPE).

Like previous node updates from Samsung, the new 10LPP fabrication process promises a range of improvements depending on what a customer is looking for. On the performance front the process is said to offer 10% higher performance at the same complexity and power, or alternatively, customers can design for an up to 15% reduction in power consumption at the same frequency and complexity. Samsung Foundry does not disclose how it managed to improve the 10LPP vs. the 10LPE, but it is logical to assume that the company had to optimize the transistor structure somehow. Samsung’s 10LPP and 10LPE technologies are still very similar from design rules and manufacturing points of view, so experience obtained with the former will be applicable to the latter.

Update 12/6: Samsung confirmed that in order to improve energy efficiency and frequency potential of the 10LPP process technology, it had to incorporate a lower-k dielectric as well as to increase transistor fin height.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
vs 10LPP
Power 60% 40% 30% ~15% ? 10%
Performance 40% 27% >10% ~10% ? ?
Area Reduction 50% 30% 30% none ? 10%

Samsung Foundry says that SoCs made using the 10LPP process technology will be used in devices to be launched early next year and onwards. The contract maker of semiconductors does not officially disclose which chips it is producing using the 10LPP process technology, but since it uses plural (“SoC products”), it all but given that there are more than one 10LPP SoC model in production. One of the candidates to be produced using the 10LPP is Samsung’s own Exynos 9 Series 9810 SoC that is expected to power the company’s 2018 flagship Galaxy S smartphones. Typically, Qualcomm also adopts Samsung’s latest process technologies along with the South Korean giant itself (to a large degree because its chips are used inside flagship Galaxy handsets too), but so far, Qualcomm has not made any announcements concerning the 10LPP.

Keeping in mind that while Samsung Foundry’s LPE process technologies are used primarily by Samsung itself and a very limited number of its customers, the LPP processes are adopted by a considerably larger group of clients. So the launch of the 10LPP means expanded usage of the company’s 10 nm node in general. In order to meet demand, Samsung will start to make SoCs using the 10LPP in its new S3 fab located in Hwaseong, Korea.

Meanwhile, the evolution of Samsung’s 10 nm node is not going to stop with the formal introduction of the 10LPP. Going forward, Samsung plans to introduce the 10LPU fabrication technology for ultra-low-power SoCs as well as the 8LPP manufacturing process for advanced SoCs. Samsung yet has to detail the 10LPU, but with the 8LPP it promises a 10% area reduction (at the same complexity) as well as a 10% lower power consumption (at the same frequency and complexity) compared to the 10LPP process due to narrower metal pitches and other optimizations.

“We will be able to better serve our customers through the migration from 10LPE to 10LPP with improved performance and higher initial yield,” said Ryan Lee, vice president of foundry marketing at Samsung Electronics. “Samsung with its long-living 10nm process strategy will continue to work on the evolution of 10nm technology down to 8LPP to offer customers distinct competitive advantages for a wide range of applications.”

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Source: Samsung

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  • HStewart - Wednesday, November 29, 2017 - link

    Does anybody know what Transistor count will be this process and how it compares to existing processes?
  • MrSpadge - Wednesday, November 29, 2017 - link

    Anything between 0 and a few 10 billions, depending on how much chip area customers are willing to pay for. Did you want to ask for transistor density? That would also depend on the mix of transistor types, but is arguably somewhere between Intels 14 nm and 10 nm.
  • HStewart - Thursday, November 30, 2017 - link

    That is what I heard also - that it more than Intel 14 nm but less than Intel's up and coming 10nm.

    Intel is actually very smart with there process where they allow different size chips, for example CPU and GPU can be on 10nm will IO components can be on 14nm or even 22nm. This actually keeps the cost down instead having everything on 10nm.
  • Santoval - Thursday, November 30, 2017 - link

    Intel appears to have been too ambitious with their 10nm node, where they managed to pack 101 million transistors inside a mm^2, which is why it was delayed that much. I doubt the others will manage to go beyond that at 7nm (or even match it, perhaps), not in that node's first generation anyway. Of course all that matters is that Intel ships 10nm CPUs (hopefully in Q1 2018).
  • Wilco1 - Thursday, November 30, 2017 - link

    TSMC and Samsung 7nm are 20-30% denser than Intel 10nm. TSMC has started production of 7nm and should enter mass production within 6 months.

    However I think it is misleading just consider maximum theoretical transistor density. How you use the transistors matters too. See eg. where AMD manages to pack transistors tighter despite using a less advanced process.
  • Lodix - Wednesday, November 29, 2017 - link

    It has around 50MTr/mm^2 similar to TSMC's 10nm and 30-40% more dense than Intel's 14nm++.
  • HStewart - Wednesday, November 29, 2017 - link

    But Intel's 10nm is suppose to be around 100nm which could explain why it been delay so much.
  • atragorn - Wednesday, November 29, 2017 - link

    Samsung yet has to detail the 10LPU,
  • SquarePeg - Thursday, November 30, 2017 - link

    So in other words, Snapdragon 845 inbound with Galaxy S9/S9+ early exclusivity.

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