While you're overly optimistic about the frequency of a server CPU as 4.5GHz would be well outside the performance per Watt optimum even for a 7nm CPU, you are grossly underestimating the core count. EPYC2 or Rome will have at least 48c/96t and most rumours suggests 64c/128t on a single package for the top SKUs.
The best they could do is 3.8 - 3.9 GHz base, ~4.5 GHz turbo for all clocks (for 32 cores, make that 4.2 - 4.3 GHz turbo for 48 cores and, if they do release 64-core packages, 4 - 4.1 GHz turbo for all clocks, with a corresponding drop in base clocks for all) and perhaps up to a 4.8 - 4.9 GHz turbo for 1 & 2 cores. And that assumes that they would spend most of the 7nm node's additional power efficiency to higher clocks rather than other areas (i.e. in reworking the architecture), which is not at all certain. Frankly the above clocks would make more sense for a move of the Zen/Zen+ to 7nm, rather than Zen 2, which will sport a new architecture. How new it remains to be seen.
Has TSMC historically produced "better" chips at given size relative to GloFo? or are these results of fallacies in the AT comment section I took to be fact?
Transistor performance is *arguably* more important for CPUs Transistor density is *arguably* more important for GPUs So it might be that TSMC is better at building GPUs and GF better at building CPUs
I haven't seen any evidence for it either way - just not aware of any CPU designs clocking 4GHZ+ out of TSMC, but that doesn't necessarily mean they can't. Rome would be good counter evidence.
EPYC used the same die as Ryzen for a bunch of reasons:
AMD claimed that it was cheaper to fab 4 ~200mm**2 chips than 1 ~700mm*2 chip. This might be GloFo specific and TSMC won't have a problem with a bigger chips (and obviously each core will be smaller in 7nm). AMD didn't want to spend the money on multiple masks (although obviously they made another for their ALUs) AMD's data bus/ring sucked so much that multiple CPUs wired together didn't lose performance. If they are on one big chip (which is sounds like), presumably they've fixed their data fabric.
Even if TSMC didn't have a problem with making huge monolithic dies AMD would have, since TSMC would charge them much more for each huge monolithic die than each 4 smaller dies, which would eat at AMD's margins. And that's because yields of huge dies are quite lower and they are more difficult to manufacture.
Putting aside the non-issue of a monolithic Epyc or top-core TR die, each Zeppelin die will be smaller at 7nm only if the cores are the same or up to 12 (for 6 cores per CCX). If AMD moves to 16-core Zeppelin dies (with either two 8-core CCX blocks or, quite unlikely, four 4-core ones), either for Epyc only or also for TR and Ryzen, the dies will be either the same size (assuming exactly twice the density of both the FEOL and BEOL stack) or a bit larger (assuming a bit lower than double density).
So, if AMD can afford to move to 16-core dies, die-size and yield wise, they will. If not they will max out at 12-core dies and a 48-core Epyc. The question is, if they can only afford 16-core dies for Epyc, if they are going to fab both 12-core and 16-core dies, which would add to design costs but would save precious die space (from less disabling of cores). Designing both a 6-core CCX and an 8-core one would further inreace design costs.
It may not be better in terms of technical feature set. That is up for debate, because GF and TSMC have different focus on 7nm HP. But one thing for sure is TSMC has MUCH higher 7nm capacity then GF. I have been wondering why they didn't do this earlier, or may be they were being much more conservative.
Fabbing EPYC 2 with TSMC meant AMD won't have its hand tied by GF capacity, which is currently sharing with Vega, Ryzen etc. The Chinese Joint venture are producing EPYC with TSMC anyway, so there are some synergy in there as well.
Considering EYPC aren't even moving much in terms of market share but are already 60% of Consumer Desktop / Laptop / CPU + GPU Ships combined, as shown in the latest quarter results, which means AMD are currently selling lots of EPYC, and likely already constrained by GF. Intel DC segment is 10x the size of current AMD, with Intel 's 10nm behind, and their Icelake IPC improvement also delayed well into 2020. Zen 2 / EPYC 2 will be in a perfect scenario. Lisa likely don't want to waste this chance for whatever Waffer agreement they have with GF, the consumer division will have to work harder to fill those demand, which I assume won't be much of a problem.
To your last point I assume AMD they already met there wafer agreement this year and if Gloflo outs Ryzen (Zen 2) next year then GloFlo will have its hands full. Lisa Su is making all the right moves imo.
TSMC is a natural choice for a chip like this. Low volume, large die. The volume of Threadrippers is negligible to offset their obligations with GloFo, and TSMC is far better suited to producing monolithic dies.
Large die? The die size is the same as the Ryzen dies. There's just 4 of them like in the next gen Threadripper. However, at 7nm most people expect those dies to have 12 or even 16 cores each while being the same small size as the current ones.
Umm Rome (EPYC 2nd Gen) isn't a large monolithic die, just like 1st Gen wasn't. It's 4x small chiplets linked via Infinity Fabric just like last time. They'll use the exact same SP3 socket / MCM package as currently.
Is this really confirmed? The math should be the same and I'd certainly expect that AMD would use MCM if using GloFo fabs. 64 cores should put it on the edge of what TSMC could do on one die, so they may well break it up into 4 dice. Of course they could always use an interposer (assuming they have a better network fabric and can justify the cost).
Breaking it up likely also means that they haven't improved the network fabric. That's sad, but not unexpected (tons of server jobs don't need it, like pretty much all of AWS). I suspect that if they improved the fabric, they'd have 16-32 cores on each die, and only go MCM for really big monsters (or even using some HBM-like interposer).
could not agree more, she REALLY got AMD "back on track" here is hoping she got her fists on the Radeon team as well...I have never ever though Radeons were as "trash" as people claim them to be, sure performance could be higher here and there in certain generations, but they are good all rounders and spectacular at some other things and do not "mislead" nearly as badly as Ngreedia does.
anyways, I have been "devoted" radeon fan since AMD took them over, (kind of) at least they are well built and they do not dumb down the component selection on the capacitors etc and "cheap out" by just using half arse hardware/software "tricks" to throttle them down to "attempt" to keep them from cooking themselves.
do not have the coin myself (yet) but very much looking forward to the REAL Ryzen 2 (AMD did stupid naming for Ryzen 2xxx generation, they should have stuck with Ryzen + and the number, this way here it does not cause unneeded confusion when Ryzen 2 on 7nm launches..I doubt it, but here is hoping pricing is a wee tad more fair then Ryzen 1xxx and Ryzen 2xxx was/is for us Canadian folks and automatic "Canada" price higher then should be crud ^.^...I hate them marketing folks, they are "putzes"
GF's 7nm is being designed to be better than TSMC's 7nm. However, TSMC has 7nm in HVM for a few months already, and while GF says they are on track with 7nm in HVM early 2019, that is still a promise. And AMD is in a big race vs. Intel, intel usually ships its server processors last on a given manufacturing node because Intel's server chips are huge monolithic dies and need to go into production when yields are really high. AMD with their CCX architecture relies on smaller dies so they do not need yields as high. If you consider CCX + TSMC, AMD is taking every chance it has against Intel. This is a huge opportunity for them and it is possible that TSMC will have 5nm out around the time Intel will have an answer to Rome. So, sticking with TSMC may mean staying ahead of Intel for many generations to come (GF on the other hand will skip 5nm).
TSMC is the leading foundry right now, they have passed Intel and are expected to maintain their lead at least until 3nm. Epyc on TSMC is a huge headache for Intel.
Nobody knows that but the customers. My guess would be that GF specializes in yield (they were AMD's fab division, and AMD was focused on yield) whereas TSMC focuses on performance/density (because they're selling risk wafers, so who gives a fuck what the yield is the customer buys by the wafer).
This is sort of born out by rumored Zeppelin yields and historical yield problems at TSMC with large GPU's.
From an absolute perspective, TSMC's processes tend to better density characteristics objectives (metrics like gate pitch, etc, favor TSMC).
I don't think TSMC has ever fabbed a very high clocking (>4 GHz) part in commercial volumes, so it may be that GF has an advantage there as well.
The more interesting point to be made, this explains why Ryzen 2 arrives after Rome. It's safe to assume Ryzen 2 is at GloFo so it arrives when GloFo is ready.. It's also likely that AMD would stick with TSMC and N7+ beyond Rome and have it in 2020 when Intel moves server to 10nm.
Well it also makes sense that EPYC iterates slower than Ryzen due to the long validation cycles in enterprise. No point in making an Zen+ EPYC if the Zen based products are just now reaching market. Just skip it and put the effort into making Zen2 EPYC.
They don't currently fab anything on the scale that TSMC does as far as die size goes, but NVIDIA and AMD have both run GPU designs through Samsung fabs in the last couple years, so they are capable of doing so.
IIRC AMD paid GF a lot of money two years ago to get flexibility with the wafer agreement. It got rid of a lot of the restrictions it imposed on AMD in terms of time-to-market and volume manufacturing.
Since TSMC already has 7nm production going and GloFlos is a little way out. I'm sure GloFlos 7nm process will scale up to higher frequencies like 5Ghz+ but that really isn't needed in the server market. Shifting over to TSMC to come to market faster is brilliant. I am pretty sure Intel execs are cursing at this news.
Ultimately, I'm thinking that the fact that AMD is producing the Rome CPUs at TMSC - means that they probably ARE meeting their quota with GF via the Ryzen/Vega chips. Thus, no penalties, especially since GF has been nearly at capacity.
With the growth that was apparent in enterprise on the latest AMD report, I think they really want to get a bunch of Epyc server CPUs ready for market now they had some time to validate them.
I believe that this decision has mainly to do with TSMC being able to do 7 nm now, whereas GloFo isn't ready yet, AND by going with TSMC, AMD will have bragging rights over Intel on the "nm front". With this move, AMD can point to their big server chips being manufactured in a 7 nm process, even after Intel gets their server chips in 10 nm up-and-running. If AMD had waited for GloFo to get 7 nm online, no such differentiator in time for ZEN2 EPYC's launch.
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JoeyJoJo123 - Thursday, July 26, 2018 - link
Zen2 EPYC sounds great. Can't wait for Zen2 arch to come to Threadripper platforms as well.jklw10 - Thursday, July 26, 2018 - link
32 core epyc with 4.5 ghz? yes please :DSaturnusDK - Thursday, July 26, 2018 - link
While you're overly optimistic about the frequency of a server CPU as 4.5GHz would be well outside the performance per Watt optimum even for a 7nm CPU, you are grossly underestimating the core count. EPYC2 or Rome will have at least 48c/96t and most rumours suggests 64c/128t on a single package for the top SKUs.Death666Angel - Friday, July 27, 2018 - link
Single or quad core turbo maybe? :)Santoval - Monday, July 30, 2018 - link
The best they could do is 3.8 - 3.9 GHz base, ~4.5 GHz turbo for all clocks (for 32 cores, make that 4.2 - 4.3 GHz turbo for 48 cores and, if they do release 64-core packages, 4 - 4.1 GHz turbo for all clocks, with a corresponding drop in base clocks for all) and perhaps up to a 4.8 - 4.9 GHz turbo for 1 & 2 cores.And that assumes that they would spend most of the 7nm node's additional power efficiency to higher clocks rather than other areas (i.e. in reworking the architecture), which is not at all certain. Frankly the above clocks would make more sense for a move of the Zen/Zen+ to 7nm, rather than Zen 2, which will sport a new architecture. How new it remains to be seen.
K_Space - Thursday, July 26, 2018 - link
Has TSMC historically produced "better" chips at given size relative to GloFo? or are these results of fallacies in the AT comment section I took to be fact?Arnulf - Thursday, July 26, 2018 - link
TSMC is actually producing huge monolithic chips (such as NVidia GPUs) for years now.Zeppelin dies manufactured by GF (employed in 1st generation Epyc CPUs) are what, one third the of the area of largest GPU/AI chips?
Spoelie - Friday, July 27, 2018 - link
Transistor performance is *arguably* more important for CPUsTransistor density is *arguably* more important for GPUs
So it might be that TSMC is better at building GPUs and GF better at building CPUs
I haven't seen any evidence for it either way - just not aware of any CPU designs clocking 4GHZ+ out of TSMC, but that doesn't necessarily mean they can't. Rome would be good counter evidence.
wumpus - Friday, July 27, 2018 - link
EPYC used the same die as Ryzen for a bunch of reasons:AMD claimed that it was cheaper to fab 4 ~200mm**2 chips than 1 ~700mm*2 chip. This might be GloFo specific and TSMC won't have a problem with a bigger chips (and obviously each core will be smaller in 7nm).
AMD didn't want to spend the money on multiple masks (although obviously they made another for their ALUs)
AMD's data bus/ring sucked so much that multiple CPUs wired together didn't lose performance. If they are on one big chip (which is sounds like), presumably they've fixed their data fabric.
Santoval - Monday, July 30, 2018 - link
Even if TSMC didn't have a problem with making huge monolithic dies AMD would have, since TSMC would charge them much more for each huge monolithic die than each 4 smaller dies, which would eat at AMD's margins. And that's because yields of huge dies are quite lower and they are more difficult to manufacture.Putting aside the non-issue of a monolithic Epyc or top-core TR die, each Zeppelin die will be smaller at 7nm only if the cores are the same or up to 12 (for 6 cores per CCX). If AMD moves to 16-core Zeppelin dies (with either two 8-core CCX blocks or, quite unlikely, four 4-core ones), either for Epyc only or also for TR and Ryzen, the dies will be either the same size (assuming exactly twice the density of both the FEOL and BEOL stack) or a bit larger (assuming a bit lower than double density).
So, if AMD can afford to move to 16-core dies, die-size and yield wise, they will. If not they will max out at 12-core dies and a 48-core Epyc. The question is, if they can only afford 16-core dies for Epyc, if they are going to fab both 12-core and 16-core dies, which would add to design costs but would save precious die space (from less disabling of cores). Designing both a 6-core CCX and an 8-core one would further inreace design costs.
iwod - Thursday, July 26, 2018 - link
It may not be better in terms of technical feature set. That is up for debate, because GF and TSMC have different focus on 7nm HP. But one thing for sure is TSMC has MUCH higher 7nm capacity then GF. I have been wondering why they didn't do this earlier, or may be they were being much more conservative.Fabbing EPYC 2 with TSMC meant AMD won't have its hand tied by GF capacity, which is currently sharing with Vega, Ryzen etc. The Chinese Joint venture are producing EPYC with TSMC anyway, so there are some synergy in there as well.
Considering EYPC aren't even moving much in terms of market share but are already 60% of Consumer Desktop / Laptop / CPU + GPU Ships combined, as shown in the latest quarter results, which means AMD are currently selling lots of EPYC, and likely already constrained by GF. Intel DC segment is 10x the size of current AMD, with Intel 's 10nm behind, and their Icelake IPC improvement also delayed well into 2020. Zen 2 / EPYC 2 will be in a perfect scenario. Lisa likely don't want to waste this chance for whatever Waffer agreement they have with GF, the consumer division will have to work harder to fill those demand, which I assume won't be much of a problem.
FreckledTrout - Thursday, July 26, 2018 - link
To your last point I assume AMD they already met there wafer agreement this year and if Gloflo outs Ryzen (Zen 2) next year then GloFlo will have its hands full. Lisa Su is making all the right moves imo.Samus - Thursday, July 26, 2018 - link
TSMC is a natural choice for a chip like this. Low volume, large die. The volume of Threadrippers is negligible to offset their obligations with GloFo, and TSMC is far better suited to producing monolithic dies.SaturnusDK - Thursday, July 26, 2018 - link
Large die? The die size is the same as the Ryzen dies. There's just 4 of them like in the next gen Threadripper. However, at 7nm most people expect those dies to have 12 or even 16 cores each while being the same small size as the current ones.Cooe - Friday, July 27, 2018 - link
Umm Rome (EPYC 2nd Gen) isn't a large monolithic die, just like 1st Gen wasn't. It's 4x small chiplets linked via Infinity Fabric just like last time. They'll use the exact same SP3 socket / MCM package as currently.wumpus - Friday, July 27, 2018 - link
Is this really confirmed? The math should be the same and I'd certainly expect that AMD would use MCM if using GloFo fabs. 64 cores should put it on the edge of what TSMC could do on one die, so they may well break it up into 4 dice. Of course they could always use an interposer (assuming they have a better network fabric and can justify the cost).Breaking it up likely also means that they haven't improved the network fabric. That's sad, but not unexpected (tons of server jobs don't need it, like pretty much all of AWS). I suspect that if they improved the fabric, they'd have 16-32 cores on each die, and only go MCM for really big monsters (or even using some HBM-like interposer).
Dragonstongue - Thursday, July 26, 2018 - link
could not agree more, she REALLY got AMD "back on track" here is hoping she got her fists on the Radeon team as well...I have never ever though Radeons were as "trash" as people claim them to be, sure performance could be higher here and there in certain generations, but they are good all rounders and spectacular at some other things and do not "mislead" nearly as badly as Ngreedia does.anyways, I have been "devoted" radeon fan since AMD took them over, (kind of) at least they are well built and they do not dumb down the component selection on the capacitors etc and "cheap out" by just using half arse hardware/software "tricks" to throttle them down to "attempt" to keep them from cooking themselves.
do not have the coin myself (yet) but very much looking forward to the REAL Ryzen 2 (AMD did stupid naming for Ryzen 2xxx generation, they should have stuck with Ryzen + and the number, this way here it does not cause unneeded confusion when Ryzen 2 on 7nm launches..I doubt it, but here is hoping pricing is a wee tad more fair then Ryzen 1xxx and Ryzen 2xxx was/is for us Canadian folks and automatic "Canada" price higher then should be crud ^.^...I hate them marketing folks, they are "putzes"
ajp_anton - Friday, July 27, 2018 - link
Eh, 7nm CPUs will be Ryzen 3.Architecture - Product name
Zen - Ryzen 1000
Zen+ - Ryzen 2000
Zen2 - Ryzen 3000
mpbello - Thursday, July 26, 2018 - link
GF's 7nm is being designed to be better than TSMC's 7nm. However, TSMC has 7nm in HVM for a few months already, and while GF says they are on track with 7nm in HVM early 2019, that is still a promise.And AMD is in a big race vs. Intel, intel usually ships its server processors last on a given manufacturing node because Intel's server chips are huge monolithic dies and need to go into production when yields are really high. AMD with their CCX architecture relies on smaller dies so they do not need yields as high.
If you consider CCX + TSMC, AMD is taking every chance it has against Intel. This is a huge opportunity for them and it is possible that TSMC will have 5nm out around the time Intel will have an answer to Rome. So, sticking with TSMC may mean staying ahead of Intel for many generations to come (GF on the other hand will skip 5nm).
TSMC is the leading foundry right now, they have passed Intel and are expected to maintain their lead at least until 3nm. Epyc on TSMC is a huge headache for Intel.
Sahrin - Wednesday, August 1, 2018 - link
Nobody knows that but the customers. My guess would be that GF specializes in yield (they were AMD's fab division, and AMD was focused on yield) whereas TSMC focuses on performance/density (because they're selling risk wafers, so who gives a fuck what the yield is the customer buys by the wafer).This is sort of born out by rumored Zeppelin yields and historical yield problems at TSMC with large GPU's.
From an absolute perspective, TSMC's processes tend to better density characteristics objectives (metrics like gate pitch, etc, favor TSMC).
I don't think TSMC has ever fabbed a very high clocking (>4 GHz) part in commercial volumes, so it may be that GF has an advantage there as well.
jjj - Thursday, July 26, 2018 - link
The more interesting point to be made, this explains why Ryzen 2 arrives after Rome. It's safe to assume Ryzen 2 is at GloFo so it arrives when GloFo is ready..It's also likely that AMD would stick with TSMC and N7+ beyond Rome and have it in 2020 when Intel moves server to 10nm.
rocketscience315 - Thursday, July 26, 2018 - link
Well it also makes sense that EPYC iterates slower than Ryzen due to the long validation cycles in enterprise. No point in making an Zen+ EPYC if the Zen based products are just now reaching market. Just skip it and put the effort into making Zen2 EPYC.Death666Angel - Thursday, July 26, 2018 - link
Ryzen 2 is already launched and shipping. Do you mean Zen 2? Which will likely be Ryzen 3?jjj - Thursday, July 26, 2018 - link
Yeah i should have said Ryzen with Zen 2.Teckk - Thursday, July 26, 2018 - link
When does the Wafer Supply Agreement terminate? Also, AMD came to to Samsung by choice, does Samsung manufacture desktop powering processors?Teckk - Thursday, July 26, 2018 - link
*can't use Samsung - phone keyboards :(FullmetalTitan - Thursday, July 26, 2018 - link
They don't currently fab anything on the scale that TSMC does as far as die size goes, but NVIDIA and AMD have both run GPU designs through Samsung fabs in the last couple years, so they are capable of doing so.psychobriggsy - Monday, July 30, 2018 - link
IIRC AMD paid GF a lot of money two years ago to get flexibility with the wafer agreement. It got rid of a lot of the restrictions it imposed on AMD in terms of time-to-market and volume manufacturing.https://www.anandtech.com/show/10631/amd-amends-gl... says that the agreement terminates in 2024.
FreckledTrout - Thursday, July 26, 2018 - link
Since TSMC already has 7nm production going and GloFlos is a little way out. I'm sure GloFlos 7nm process will scale up to higher frequencies like 5Ghz+ but that really isn't needed in the server market. Shifting over to TSMC to come to market faster is brilliant. I am pretty sure Intel execs are cursing at this news.AndrewJacksonZA - Thursday, July 26, 2018 - link
"Along with AMD’s epic quarterly results"I see what you did there. :-)
bill.rookard - Friday, July 27, 2018 - link
Ultimately, I'm thinking that the fact that AMD is producing the Rome CPUs at TMSC - means that they probably ARE meeting their quota with GF via the Ryzen/Vega chips. Thus, no penalties, especially since GF has been nearly at capacity.With the growth that was apparent in enterprise on the latest AMD report, I think they really want to get a bunch of Epyc server CPUs ready for market now they had some time to validate them.
eastcoast_pete - Friday, July 27, 2018 - link
I believe that this decision has mainly to do with TSMC being able to do 7 nm now, whereas GloFo isn't ready yet, AND by going with TSMC, AMD will have bragging rights over Intel on the "nm front". With this move, AMD can point to their big server chips being manufactured in a 7 nm process, even after Intel gets their server chips in 10 nm up-and-running. If AMD had waited for GloFo to get 7 nm online, no such differentiator in time for ZEN2 EPYC's launch.